M.T. Yang

University of Toronto, Toronto, Ontario, Canada

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Publications (20)0 Total impact

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    ABSTRACT: The concept of diffusion topography engineering (DTE) is proposed and exercised on state-of-the-art 65 nm technology for the first time. Diffusion region extended over STI and therefore resulting in T-shape diffusion profile is created purposely to suppress STI stress and oxide divot. This novel technique delivers up to 33% PMOS and 22% NMOS enhancement, respectively, and results in -10% R.O. speed improvement. When combined with high-stress contact-etch-stop-layer (CESL) , a significant 27% CMOS enhancement is achieved through preferable strain superposition. Both device integrity and reliability are carefully evaluated and neither of them is adversely impacted by DTE.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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    ABSTRACT: A 60-GHz power amplifier with 14 dB gain, 5 dB simulated noise figure, and a saturated output power of +6 dBm was fabricated in a 90 nm GP process with a 9-metal digital back end. The amplifier employs two cascode stages and a common-source output stage with inductive degeneration. It has a power-added-efficiency of 6% while consuming 45 mW from a 1.5-V supply. The robustness and repeatability of the small signal and large signal performance were characterized across dies, power supply voltage, and over temperature up to 125degC. The design was also scaled to 85 GHz in 65 nm CMOS with +5 dBm P<sub>sat</sub>.
    Compound Semiconductor Integrated Circuit Symposium, 2007. CSIC 2007. IEEE; 11/2007
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    ABSTRACT: The experimental verification of CR018 wideband noise model for AMS/RF CMOS simulation was achieved using the BSIM3v3 flicker noise model, SPICE2 thermal noise model, and induced gate and bulk noises as well. Among which, independent flicker noise corner model scaling with device size was developed to enable low power design. Moreover, the corner frequency was measured experimentally and validated with model simulation. As to the high frequency thermal noise model, we measured the noise figure with varying gate length and compared with model simulations of SPICE2 and BSIM3v3. A good fit of SPICE2 is achieved using a theoretical value of gamma=2/3 even for the shortest channel length of 0.1 Sum. An effective gamma less than 2/3 derived from BSIM3v3 was obtained. In addition, we observed that the induced gate and bulk noises are important in high frequency as the device sized up. Finally, we sanity checked the developed wideband noise model with switched capacitor and VCO phase noise.
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
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    ABSTRACT: This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transceiver building blocks are provided which emphasize the need for aggressively scaled GP CMOS and low-VT transistors if CMOS is to compete with SiGe BiCMOS above 60 GHz. This requirement is in conflict with the 2005-ITRS proposal to use LP CMOS for RF applications.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
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    ABSTRACT: SiGe/Si HBT combining the integration and cost benefits of silicon has came of age as an ideal process for wireless/wired communication applications. To encompass both high-speed analog and wireless circuit applications, production-proven Spice model of HBT that allows the great amount of flexibility and provides excellent model accuracy over a broad range of applications is highly desirable. This paper reports on an unitary set of geometry-scalable, wide-band models for the HBTs of 0.18 um BiCMOS technology. Verification of the scalable model is achieved with focus on the correlations of DC, Y-parameter and fT, noise, large-signal and Monte-Carlo of mismatch and statistical covers a wide range of product requirement.
    VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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    ABSTRACT: A low-power 40-Gb/s decision circuit for fiber-optic and mm-wave analog-to-digital converter applications was implemented in two 90-nm processes from two different foundries. The circuit uses a MOS-CML master-slave latch topology with only two vertically stacked transistors. It combines low and high-V<sub>T</sub> MOSFETs to allow for operation from a 1.2-V supply, without compromising speed. Full-rate retiming with jitter reduction and 7 ps rise/fall times is demonstrated at 37 Gb/s and 40 Gb/s from 1.2 V and 1.5 V, respectively. The entire decision circuit dissipates 130 mW from 1.2 V, with a record low power consumption of 10.8 mW per latch
    Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European; 10/2006
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    ABSTRACT: 60-GHz power (PA) and low-noise (LNA) amplifiers implemented in a 90-nm RF-CMOS process with thick 9-metal layer copper backend and transistor f<sub>T</sub>/f<sub>max</sub> of 140GHz/170GHz are reported. The PA operates from a 1.5V supply with 5.2dB power gain, a 3-dB bandwidth >13GHz, a P<sub>1dB</sub>of +6.4dBm with 7% PAE and a saturated output power of +9.3dBm at 60GHz. The LNA features 14.6dB gain, an IIP3 of -6.8dBm, and a simulated NF of 4.5dB, while drawing 16mA from a 1.5V supply. Both circuits employ inductors which reduce the total PA and LNA die sizes to 0.35 times 0.43 mm<sup>2</sup> and 0.35 times 0.40 mm<sup>2</sup>, respectively
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE; 07/2006
  • C.C. Chen, A. Chin, M.T. Yang, S. Liu
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    ABSTRACT: High-performance band-pass filters are demonstrated on VLSI incorporating interconnects and high resistivity substrate. The resonating frequency of this coupled-line filter increases not only with the increasing spacing-gap but are with increasing IDM thickness. This band-pass filter, low insertion loss and wide bandwidth characteristics, are suitable for the advanced wireless system. The established equivalent circuit model for this band-pass filter corresponds with the measured results and provides effectively RF passive components embedded into system-on-chips
    Interconnect Technology Conference, 2006 International; 07/2006
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    ABSTRACT: Statistical characterization of low-frequency noise enables the prediction of 1/f noise with dispersions. The impact of downscaling on the low-frequency noise performance of foundry AMS/RF CMOS technology is thus evaluated. Meanwhile, a novel modeling approach uses Monte-Carlo simulation is developed which includes statistical variations of individual device to capture the fluctuations in frequency and amplitude of the low-frequency noise of deep-sub-micrometer CMOS
    Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on; 02/2006
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    ABSTRACT: On-chip microstrip and coplanar waveguide structures were designed and fabricated in RF CMOS foundry processes. The wideband transmission line characteristics such as characteristic impedance, attenuation constant, propagation delay, and their electrical RLC parameters were evaluated based on S-parameter measurements in the millimeter-wave range. In addition, a SPICE-compatible RLC lumped element model including the skin-effect and the substrate RC network is employed to account for transmission line effects in interconnect over a wide frequency range up to 110 GHz.
    Microwave Symposium Digest, 2005 IEEE MTT-S International; 07/2005
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    ABSTRACT: An investigation of the flicker noise, by exploring 0.13 μm and beyond MS/RF CMOS technology, was carried out for wireless system-on-a-chip (SOC) applications. The on-chip flicker noise of various components are characterized and accurately modeled. The feasibility of deep N-well isolation to suppress substrate coupling of analog nodes from digital clock noise is also demonstrated.
    Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on; 05/2005
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    ABSTRACT: Multiple variants of SiGe HBTs, using selected collector implants, suitable for wired and wireless applications were explored. The RF/analog characteristics of HBTs featured with fT/BV<sub>CEO</sub> values of 130 GHz/2.3 V, 80 GHz/3.4 V and 60 GHz/ 4.8 V were characterized. The dependence of bias, temperature, frequency, noise, power, and geometry were investigated to provide designers with appropriate performance-breakdown design coverage and flexibility.
    Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting; 10/2004
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    ABSTRACT: As scaling down the MOSFET, the f<sub>t</sub> keeps increasing but the minimum noise figure (NF<sub>min</sub>) is difficult to scale down due to the increasing gate resistance. In this study, the NF<sub>min</sub> can be continuously reduced to 0.13 μm technology node (80 nm gate length) by optimizing finger number and channel width. Excellent NF<sub>min</sub> of only 0.87 dB is measured with 4μm finger width and multiple 72 fingers. In addition, high associated gain (22.5dB), low RF noise (1.0 dB), and low power can be simultaneously achieved in 0.13 μm mode MOSFETs using only 6 fingers that is impossible in 0.18μm case. We have also predicted the future scaling trend of RF noise beyond 0.13μm mode from measured data and well calibrated Fukui's equation.
    Microwave Symposium Digest, 2004 IEEE MTT-S International; 07/2004
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    ABSTRACT: A compact model capable of simulating both DC and RF characteristics is highly desirable. This work is the first report of an extensive experimental evaluation of the accuracy of the BSIM4 model at high frequencies using a 0.13 μm RF-CMOS process. The accuracy of the model is verified on both N-channel and P-channel devices through small-signal S-parameter measurements up to 50 GHz, 1/f noise measurements, and noise figure measurements in the 2-GHz to 6-GHz range.
    Microwave Symposium Digest, 2004 IEEE MTT-S International; 07/2004
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    ABSTRACT: The paper reports on the first unitary set of geometry-scalable, wide-band compact models for all the components of a 0.13 μm RF CMOS technology and which are valid up to 50 GHz. Verification of the active and passive device models is achieved at the device level as well as by comparing measurements and simulation results of the S-parameter response and jitter generation of high-speed circuits operating above 10 GHz from a single 1.2 V supply.
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE; 07/2004
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    ABSTRACT: A new method to directly extract the MOSFET small-signal parameters ncluding non-quasi-static effects - from Z and Y parameter measurements is presented. This technique is employed to generate a scalable BSIM3v3 model valid for standard, low and high-threshold p- and n-channel MOSFETs at frequencies up to 50 GHz. The model accurately captures cutoff frequency degradation for unit gate finger widths below 1 μm and was employed to verify the measured jitter of a 10-Gb/s MOS-CML output driver.
    Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on; 04/2004
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    ABSTRACT: Special test structures using separated source and bulk contacts with the 3<sup>rd</sup> GSG probe for the substrate bias are described. These test structures allow characterizing 4-terminal MOSFETs with a standard two-port Network Analyzer. The high-frequency behavior of bulk effect in MOSFETs is studied at different bias conditions for a 0.18 μm RF CMOS technology. Measurement result of RF NMOSFET shows that a good accuracy of the 4-terminal RF MOSFET modeling is achieved. The validity and accuracy of our approach is verified and analyzed from two-port Y-parameter results.
    Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on; 04/2004
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    ABSTRACT: Current foundry technology menus are so rich that they are sufficient to provide single chip solutions to a wide variety of desktop, portable and communication systems. At 130-nm and 90-nm generations, many of the device characteristics are no longer a straightforward extension of past generations. Special attention should be made for mixed-signal chip design. A judicious choice of devices and careful trade-off between version options should be made to maximize the benefit from the latest foundry offerings.
    Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003; 10/2003
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    ABSTRACT: Proton bombardment has been used to boost the on-chip inductor quality factor and to also improve the frequency response. In this paper we demonstrated these advantages using the 0.13μm and 0.18μm RF CMOS processes. Based on the model, we evaluated how the performance improved using bombardment technology. A simultaneously impressive increase both in the peak Q-value and the optimal frequency have been evidenced due to its significantly reduced substrate parasitic effect as a result of higher substrate resistivity. This can be considered as a solution to integrate inductor on a Si substrate.
    Microwave Symposium Digest, 2003 IEEE MTT-S International; 07/2003
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    ABSTRACT: A broadband small-signal model suitable for deep sub-micron MOSFET high frequency applications and its parameter extraction have been proposed and demonstrated. Using a 110 GHz millimeter wave S-Parameter measurement, we directly extracted the parameters and fitted very well within a broad range from 45 MHz up to 110 GHz. This is a state-of-the-art technique that demonstrates the model up to 110 GHz and can be considered as an initial method for an optimization procedure to be used for more complete models.
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE; 07/2003

Publication Stats

153 Citations

Institutions

  • 2004–2007
    • University of Toronto
      • The Edward S. Rogers Sr. Department of Electrical and Computer Engineering
      Toronto, Ontario, Canada
  • 2006
    • National Chiao Tung University
      • Institute of Electrical Control Engineering
      Hsinchu, Taiwan, Taiwan