[Show abstract][Hide abstract] ABSTRACT: Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of −5–14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.
[Show abstract][Hide abstract] ABSTRACT: Experimental results show that the V <sub>OC</sub> of layered heterojunction (HJ) organic photovoltaic (PV) cells behaves with a very weak dependence on the electrodes. However, the V <sub>OC</sub> of bulk HJ PV cells behaves with a strong dependence on the electrodes. In this paper, an explanation for the different behaviors of V <sub>OC</sub> on the electrodes is proposed. It is found that the V <sub>OC</sub> of the two types of PV cells follows the same mechanism and is mainly determined by the light-injected carriers at the donor/acceptor (D/A) interface and the electrodes. However, the distinct device structures make the boundary conditions in layered and bulk HJ PV cells different, which leads to the different dependences of V <sub>OC</sub> on the electrodes. The layered HJ PV cells have geometrically Â¿flatÂ¿ D/A and metal/organic (M/O) interfaces (the interface near the electrode), which makes the effective thickness from the D/A interface to the M/O interface large. Thus, there is a low electric field at the M/O interface and, then, a very small barrier lowering. Under this condition, the light-injected carriers at the D/A interface tend to Â¿pinÂ¿ the Fermi level of the electrodes. As a result, V <sub>OC</sub> shows only a very weak dependence on the work function of the electrodes. However, the formation of the interpenetrating network in bulk HJ PV cells greatly decreases the D and A domain dimensions and induces the ambipolar carrier distribution in the blend layer. This will cause very large barrier lowering at the M/O interface when there is a high barrier. Under this condition, the light-injected carriers at the D/A interface can no longer Â¿pinÂ¿ the electrode Fermi level. Thus, a strong dependence of V <sub>OC</sub> on the electrodes for bulk HJ PV cells is observed.
IEEE Transactions on Electron Devices 03/2010; · 2.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Metal-insulator-metal (MIM) capacitors fabricated with (8%) La-doped HfO<sub>2</sub> single layer as well as HfLaO/ LaAlO<sub>3</sub>/HfLaO multilayer dielectric stack are demonstrated. While the La-doped HfO<sub>2</sub> single layer is crystallized at 420<sup>??</sup>C annealing, HfLaO/LaAlO<sub>3</sub>/HfLaO multilayer dielectric stack remains amorphous. A high dielectric-constant value of 38 can be obtained when 8% La-doped HfO<sub>2</sub> is crystallized into cubiclike structure. However, it is observed that the linearity of MIM capacitor is degraded upon crystallization. The multilayer film has lower average dielectric constant but shows low quadratic voltage linearity of less than 1000 ppm/V<sup>2</sup> up to a capacitance density of 9 fF/??m<sup>2</sup> . It is observed that the HfLaO single-layer MIM is suitable for the applications with requirements of high capacitance density and robust reliability, while the multilayer MIM is suitable for a precision circuit.
IEEE Electron Device Letters 02/2010; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Lanthanum-based high-kappa dielectrics ( LaAlO x and LaHfO x ) are systematically investigated as blocking oxide in charge-trap-type flash memory devices. Compared to Al<sub>2</sub>O<sub>3</sub> blocking oxide, LaAlO x not only exhibits faster program speed, wider V <sub>th</sub> window, and more robustness to voltage stress but also has better retention performance when the temperature is below 120degC, particularly at 85degC . In contrast, although further improvements in V <sub>th</sub> window and robustness are achieved using a higher permittivity dielectric LaHfO x , its retention performance is poor. It is found that the retention property is critically determined by the conduction band offset of a blocking oxide. This is caused by the shallow trapping energy depth inside the nitride which is calculated to be 0.6-0.75 eV below the conduction band edge.
IEEE Transactions on Electron Devices 12/2009; · 2.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Aluminum-doped gadolinium oxides GdAlO x are proposed as a blocking oxide layer in charge-trap-type flash memory cell devices. Greatly improved operation speed and charge retention properties have been demonstrated, compared to conventional Al<sub>2</sub>O<sub>3</sub> blocking layer. The optimization of Al percentage in GdAlO x , as well as charge loss mechanism in the memory cell device, has also been systematically studied.
IEEE Transactions on Electron Devices 12/2009; · 2.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: It is demonstrated that HfO<sub>2</sub> films can have much higher dielectric-constant values than the usual reported value of 20-24 by optimized incorporation of lanthanum element and crystallization to cubic structure. When HfO<sub>2</sub> with 8% La is crystallized into cubic structure, the film exhibits the kappa value of ~38 which is the highest among ever reported HfO<sub>2</sub> -based high-kappa dielectrics. The increased kappa value of HfO<sub>2</sub> with 8% La enables the leakage current to be reduced more than one order of magnitude lower, compared to amorphous-phase HfO<sub>2</sub> under the same electric field. The dependence of film thickness and annealing temperature on the cubic crystallization is also reported.
IEEE Electron Device Letters 07/2009; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: We demonstrated, for the first time, p-MOSFETs (L<sub>G</sub> ges 40 nm) with SiGe/Si core/shell channel integrated on bulk Si using a CMOS-compatible top-down processes. The Omega-shaped nanowire (NW)-like channels comprised of ~12-nm-thick inner SiGe core and 4-nm-thick outer Si shell. The devices exhibited good subthreshold characteristics (with SS ~128 mV/dec), suggesting successful surface passivation of the SiGe NW body by the outer Si capping layer. Drive currents of ~167 muA/mum is achieved, which is 15% enhancement over the reference Si-channel devices fabricated by the same process. Double g<sub>m</sub> peaks are observed at low drain bias for the core/shell SiGe NW devices, confirming the quantum confinement of holes in the SiGe inner core.
IEEE Electron Device Letters 05/2009; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A significant increase in open circuit voltage (VOC) is obtained in the polymer-fullerene bulk heterojunction solar cell by using the e-beam deposited Al cathode. Compared with the device with the thermal evaporated Al cathode, an obvious enhancement of VOC from 596 to 664 mV is obtained, which makes the overall device power conversion efficiency improved by 12.4% (from 3.79% to 4.26%). Electrical characterizations suggest that the energetic particles in the e-beam deposition induce deep interface hole traps in the poly(3-hexylthiophene-2,5-diyl) (P3HT), while leaving the fullerene unaffected. The deep trapped holes near the P3HT/cathode interface can induce the image negative charges in the cathode and thus form “dipoles.” These dipoles lead to the lowering of the Al effective work function and cause the enhancement of VOC.
[Show abstract][Hide abstract] ABSTRACT: This letter demonstrates successful integration of Gate-All-Around (GAA) nanowire (NW) transistors with low-resistivity metallic NW point contacts at source/drain extensions. Ultrascaled GAA silicon NW transistors with gate lengths down to 8 nm have been achieved, exhibiting good performance among the NW FETs reported to date. Compared to the reference devices, the metallic contact NW devices show 580% enhancement in I <sub>ON</sub> from 103 to 705 muA/mum , at a fixed I <sub>OFF</sub> of 10 nA/mum . Nickel silicide resistivity for ultrathin films is also investigated in this letter for the integration of salicided source/drain extensions with the GAA NW process. Experimental results show that 4 nm of deposited Ni is suitable for forming NW contacts with 10-nm diameters, which is thin enough to avoid oversilicidation while meeting the low-resistivity requirements.
IEEE Electron Device Letters 03/2009; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A simple and cost-effective single metal gate scheme was successfully demonstrated to form gate-all-around (GAA) nanowire FETs with optimized dual V<sub>T</sub> for low power CMOS applications. FUSI gate-induced stress effects were shown to be of great relevance to device performance. At an I<sub>Off</sub> of 20 pA/mum, superior I<sub>On</sub> of 1180 and 405 muA/mum were obtained for NFETs and PFETs at a V<sub>DD</sub> of 1.2 V.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
[Show abstract][Hide abstract] ABSTRACT: In this work, we investigate the effect of energy band profile modulation on carrier backscattering in SiGe nanowire (SGNW) heterojunction p-channel field effect transistors. The energy band profile is modulated by increasing the Ge mole fraction in nanowire channels as compared to source/drain regions using the pattern-dependent Ge condensation technique. The carrier backscattering characteristics of the fabricated heterojunction p-type SGNW transistors, extracted using a temperature-dependent analytical model, exhibited a decrease of 19% in hole backscattering coefficient in comparison to the reference planar devices with uniform Ge concentration. The reduction in backscattering coefficient is attributed to KT/q barrier layer thinning of the source-to-channel barrier for the holes as a result of the modulation in energy band profile caused by variation in Ge concentration.
[Show abstract][Hide abstract] ABSTRACT: Various metal carbides (TaC, HfC, WC, and VC) were thoroughly investigated for metal gate CMOS devices with band-edge work functions (WFs). It is found that TaC and HfC are more suitable for the CMOS device application among the various metal carbides. HfC is demonstrated to be a good candidate for NMOS because of its low WF and excellent thermal stability, while TaC Al shows a high WF and good thermal stability suitable for PMOS device application. In addition, HfC and TaC have a wide range of WF tunability using thin LaN and AlN interlayer or introduction of La and Al into the metal carbides.
IEEE Transactions on Electron Devices 10/2008; · 2.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Near-infrared photon emission spectra were obtained from the frontside of silicon nMOSFETs and pMOSFETs with a gate length of 0.13 mum and biased into saturation. These spectra were obtained using a high sensitivity in-lens spectroscopic photon emission microscope. Frontside NIR photon emission spectroscopy are performed on 0.13 mum saturated nMOSFETs and pMOSFETs at different gate and drain bias. The nMOSFETs photon emission spectra obtained are significantly different from some previously reported photon emission spectra. The NIR photon emission spectra of the nMOSFETs and pMOSFETs have similar peaks and suggest that the electric field condition in the channels of the nMOSFETs and pMOSFETs are similar.
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the; 08/2008
[Show abstract][Hide abstract] ABSTRACT: A multilayer structure of copper phthalocyanine/poly(3-hexylthiophene-2,5-diyl): [6,6]-phenyl- C <sub>61</sub> -butyric acid methyl ester (CuPc/P3HT:PCBM) is used to extend the light absorption spectrum covering almost the entire visible spectrum. To maximize the light absorption, the total number of excitons created in the multilayer structure as a function of layer thickness of both CuPc and P3HT:PCBM is simulated by using the optical transfer matrix formalism. The solar cells with a device structure of ITO/PEDOT:PSS/CuPc/P3HT:PCBM/Al are fabricated with different layers thicknesses. The optimized solar cell with a high short circuit current density of 12.54 mA / cm <sup>2</sup> and power conversion efficiency as high as 4.13% is achieved, owing to the utilization of the second optical interference peak in the multilayer structure for the enhanced light absorption.
[Show abstract][Hide abstract] ABSTRACT: A simple method is developed to make an interpenetrating network of poly(3-hexylthiophene-2,5-diyl) (P3HT) and fullerene (C60) by mixing P3HT solution with a thermal initiator 2,2′-azobis(isobutyronitrile) (AIBN). After mild annealing, the release of nitrogen from AIBN increases the roughness of P3HT dramatically. Significant photoluminescence quenching between the roughened donor P3HT and overlaying acceptor C60 is related to the significant increment of donor-acceptor interfacial areas. Based on this interpenetrated network of P3HT/C60, more than threefold increase in the photovoltaic efficiency of devices is achieved compared with bilayer structure. Fill factor is also improved, implying good percolation path in this heterojunction structure.
[Show abstract][Hide abstract] ABSTRACT: Parasitic S/D resistances in extremely scaled GAA nanowire devices can pathologically limit the device drive current performance. We demonstrate for the first time, that S/D extension dopant profile engineering together with successful integration of low resistivity metallic nanowire contacts greatly reduces parasitic resistances. This allows 8 nm gate length GAA nanowire devices in this work to attain record-high drive currents of 3740 muA/mum.
[Show abstract][Hide abstract] ABSTRACT: A top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si<sub>0.7</sub>Ge<sub>0.3</sub>) to channel (Si<sub>0.3</sub>Ge<sub>0.7</sub>) regions, is presented. Fabricated by utilizing a pattern-size-dependent Ge-condensation technique, the SGNW heterostructure PMOS device exhibits 4.5times enhancement in the drive current and transconductance (G<sub>m</sub>) as compared to the homojunction planar device (Si<sub>0.7</sub>Ge<sub>0.3</sub>). This large enhancement can be attributed to several factors including Omega-gated nanowire structure, enhanced hole injection efficiency (due to valence band offset), and improved hole mobility (due to compressive strain and Ge enrichment in the nanowire channel).
IEEE Electron Device Letters 07/2008; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: We proposed and demonstrated a simple tandem structure of organic photovoltaic (PV) cell for efficient light harvesting. In this device structure, a soluble fullerene derivative of [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) is employed simultaneously to form a bilayer heterojunction PV subcell with the underlying copper phthalocyanine (CuPc) and a bulk heterojunction PV subcell with blended poly(3-hexylthiophene-2,5-diyl) (P3HT). In comparison with the conventional tandem structure, the omission of the semitransparent intercellular connection layer reduces the complexity of the device and the light loss. The enhanced short circuit current density (JSC = 8.63 mA/cm2) and power conversion efficiency (PCE) (2.79%) of the tandem structure are nearly the sum of those of the stand-alone cells of CuPc/PCBM (JSC = 2.09 mA/cm2, PCE = 0.43%) and P3HT:PCBM (JSC = 6.87 mA/cm2, PCE = 2.50%).