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ABSTRACT: This paper discusses the temperature dependence of the threshold voltage, electron mobility and gate leakage current for the scaled NMOS transistor, which has an interfacial SiO<sub>2</sub> layer of 0.5 nm and an ALD (atomic layer deposition) fabricated HfO<sub>2</sub> dielectric layer of 2.0 nm with a 10 nm TiN metal gate electrode covered by polysilicon.
Semiconductor Device Research Symposium, 2007 International; 01/2008
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ABSTRACT: In this work, an alternate semi-classical modeling has been numerically simulated to characterize the direct tunneling current through the two-dielectric stacks. In our modeling, a modified WKB approximation is selected in getting a more accurate tunneling probability and it's mainly determined by the kinetic energy on the propagation direction rather than the total energy.
Semiconductor Device Research Symposium, 2007 International; 01/2008
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ABSTRACT: We have developed a pulse response model of write/erase operations for SONOS NVSMs. In this model, we consider the major charge transport mechanisms are band to band tunneling and trap-assisted tunneling. The storage charges in the nitride are treated as a sheet charge at the center of the nitride films. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data.
Semiconductor Device Research Symposium, 2007 International; 01/2008
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ABSTRACT: This paper develops a quantum mechanical model for gate leakage current in scaled high-K metal-gate,NMOS transistors by considering both DT and TAT in low gate voltage regions,which can also be applied to other dual dielectric layer systems. The tunneling current is very sensitive to the low dielectric constant layer thickness. The proper control of the interfacial layer is important to continue CMOS device scaling.
Semiconductor Device Research Symposium, 2007 International; 01/2008
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ABSTRACT: We develop a quantum mechanical model for electron mobility, including Coulomb scattering of carriers and surface roughness in scaled high-K, metal-gate, NMOS transistors, which predicts an increase in Coulomb scattering mobility and a slow decrease of surface roughness mobility with increasing the gate voltage. The total mobility is limited by the bulk mobility because of the need for highly-doped substrates for scaled 45nm node transistors.
Semiconductor Device Research Symposium, 2007 International; 01/2008
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ABSTRACT: We describe the development of a unique, high-performance, CMOS amplifier microchip for patch clamp experiments in biological cells. Understanding single ion channel behavior is crucial for the development of pharmaceutical drugs and their interactions with biomolecular species. The microchip amplifies transient pA currents to volts (i.e. a transimpedance amplifier of more than 100 GOmega) and is part of our overall program to develop an integrated patch-clamp system for both single ion channel characterization and whole cell characterization. The chip requires less than 100 times 100 sq. mils, operates from plusmn5 V and can faithfully reproduce transient ion channel pulses in the picoampere range. An overview of the design, simulation, fabrication, and test results if our integrated signal processing system is presented.
Life Science Systems and Applications Workshop, 2007. LISA 2007. IEEE/NIH; 12/2007
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ABSTRACT: Silicon-oxide-nitride-oxide-semiconductor (SONOS) based nonvolatile semiconductor memories (NVSMs) have been in production for over 30 years for a wide range of commercial and military applications. SONOS nonvolatile memory technology relies on charge storage in this nitride dielectric. This technology has been proven to be highly reliable in the harsh environments encountered in space and avionics applications
Non-Volatile Memory Technology Symposium, 2005; 12/2005
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Semiconductor Device Research Symposium, 2005 International; 02/2005
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Semiconductor Device Research Symposium, 2005 International; 02/2005
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Semiconductor Device Research Symposium, 2005 International; 02/2005
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ABSTRACT: We present the design, fabrication and characterization of a radiation-hardened, SONOS/CMOS 1 Mb EEPROM for space and military systems. An advanced 0.35micron, 4-level tungsten plug, CMP, high-density interconnect SONOS/CMOS technology will be described for 16 Mb SONOS/CMOS EEPROMs. SONOS/CMOS radiation-hardened EEPROMs are flight-qualified and currently employed in advanced space-borne and military systems.
Non-Volatile Memory Technology Symposium, 2004; 12/2004
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ABSTRACT: We present recent results on an integrated radiation-hardened technology, which consists of scaled silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) and bulk CMOS devices - devices designed specifically for high-density, 1 Mb EEPROMs operating in space and military environments. These devices operate at low-voltage (+7V, 2.5 ms write, -7V, 7.5 ms erase) with 10-year retention at 150C and greater than 10<sup>5</sup> erase/write cycles. We describe erase/write, retention and endurance results over a 22-250C temperature range with a tunnel oxide of 1.8 nm, 'oxynitride' of 6.5 nm, and a blocking or 'cap' oxide of 3.0 nm. These scaled SONOS devices exhibit an extrapolated 10-year memory window of 1.2V (22C) and acceptable 0.3V (150C). A SONOS retention model is presented, which includes charge loss from both direct tunneling and thermal excitation. We discuss recent results of a radiation-hardened 1Mb SONOS EEPROM and its memory cell. In addition, we discuss experiments on 'localized' charge storage with hot electron injection to write SONOS/NROM™ memory devices for higher functional density with increased retention.
Non-Volatile Memory Technology Symposium, 2004; 12/2004
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ABSTRACT: Silicon (Si) microstructures are fabricated comprising a micro-aperture (10-25 μm) in a 1.2 kÅ silicon nitride membrane connecting two microfluidic compartments. Dielectrophoretic forces are created on-chip, which guide the passage of single CHO cells through the microaperture. When a cell dielectrophoretically traverses the aperture, there is a decrease in the background ionic current. These current fluctuations are recorded under varying cell concentrations, micro-aperture sizes, and applied voltages. This work shows the feasibility of building silicon-based bioparticle detectors with nanoscale apertures for sensing the translocation of cells, proteins, and even single-stranded DNA.
Engineering in Medicine and Biology Society, 2004. IEMBS '04. 26th Annual International Conference of the IEEE; 10/2004
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ABSTRACT: For the first time, we present a SONOS retention model that incorporates both T-B and TE detrapping mechanisms. First, the influences of gate dielectric thickness, temperature and trap energy on the electron decay are discussed, based on calculations of detrapping time constants. Next, an analytical SONOS retention model is presented, considering an arbitary trap energy distribution in the silicon nitride. Finally, the model is verified with a good agreement between measured and simulated SONOS retention characteristics at temperatures from 22°C to 225°C.
Semiconductor Device Research Symposium, 2003 International; 01/2004
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ABSTRACT: The paper explores the transport of ions through a micropore as a precursor to the fabrication of an integrated planar patch-clamp measurement system on a microelectronic biochip. The paper presents the analytical model to estimate the series resistance and capacitance of a planar patch-clamp structure. The cross-sectional area, thickness of the membrane and the electrolyte concentrations are key factors in determining the series resistance of the chip. The net capacitance of the substrate is sum of the nitric-oxide layer capacitances on both sides of the wafer and that of the nitride membrane. Experimental data compared with theoretical model showed good result without any correction factor. The measured capacitance value is reasonably closer to the calculated value and the higher substrate capacitance value can be reduced by minimising the fluid area in contact with the chip.
Semiconductor Device Research Symposium, 2003 International; 01/2004
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ABSTRACT: New methods for injecting and tunneling holes and electrons into the nitride charge storage layer in non-volatile semiconductor memory (NVSM) devices were investigated. These devices store holes and electrons in traps in a nitride layer in the gate dielectric. The programming mechanisms are Fowler-Nordheim tunneling, channel hot electron (CHE) injection, hot hole injection (HHI), and direct tunneling (DT). All measurements are performed on transistors with a gate dielectric composed of a 3.5 nm tunnel oxide, 1.5 nm silicon-nitride, and a 1.7 nm blocking oxide. Charge pumping measurements are employed to characterize the interface trap density of fresh devices and monitor the generation of the new interface traps during erase/write operations.
Semiconductor Device Research Symposium, 2003 International; 01/2004
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ABSTRACT: This paper presents, a physically based inversion layer electron mobility model which takes into account the combined effects of surface roughness and coulomb scattering the two main mechanisms limiting the electron mobility in SiC MOSFETs. The MOSFET was fabricated on an aluminium-implanted surface and the transfer characteristics are analysed, then the corresponding transconductance curves are compared.
Semiconductor Device Research Symposium, 2003 International; 01/2004
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ABSTRACT: X-ray photoelectron spectroscopy (XPS) has been applied to the high-K/Si system to analyze chemical bonding structure, high-K/Si system interfaces, and interfacial silicon oxide layer formations. Also we derive an expression to determine the thickness of an interfacial oxide layer based on ARXPS electron intensity ratios and compare our results with experimental values obtained from ellipsometer measurements. In addition, we describe the formation of HfO<sub>2</sub>/Si interfacial layers together with their thermal stability and chemical structure. Finally we present valence band offset measurements obtained with HRXPS to determine band structure.
Semiconductor Device Research Symposium, 2003 International; 01/2004
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ABSTRACT: In this paper, we study about the interface charges on the operation of 4H silicon carbide static induction transistors. The structure of SIT provides high breakdown voltage and high current density between the source and drain terminals. Influence of oxide charge in the ' shoulder' oxide region on the operation of a 4H-SiC SIT has been studied. The SIT device has been modeled and simulated with varying SIT dimensions, varying gate and drain voltage.
Semiconductor Device Research Symposium, 2003 International; 01/2004
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ABSTRACT: A novel SONOS (polysilicon-oxide-nitride-oxide-silicon) nonvolatile flash memory device which uses hot hole injection through the bottom oxide for write and tunneling to/from the gate through a thin top oxide for erase, with reduced power consumption, improved retention and subthreshold swing is proposed. The dynamic characteristics along with comparisons to NROM technology, forward/reverse read I<sub>DS</sub> ∼ I<sub>GS</sub> characteristics, programming speeds and retention of SONOS device at room temperature are discussed.
Semiconductor Device Research Symposium, 2003 International; 01/2004
