W. Sansen

imec Belgium, Louvain, Flanders, Belgium

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Publications (299)203.31 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.
    IEEE Journal of Solid-State Circuits 03/2011; · 3.11 Impact Factor
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    ABSTRACT: This work presents the design and test result of a standard 0.7 μm CMOS flash analog-to-digital converter (ADC) operational in an ultra wide temperature range (UWT, room temperature down to 4.2 K). To maintain the circuit’s performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated topology and switching schemes are utilized. Test results mentioned in this text are from a single process run, no design iterations were made.
    Cryogenics 11/2009; 49(11):635-637. · 0.94 Impact Factor
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    ABSTRACT: This paper presents the first flash Analog-to-Digital Converter (ADC) in standard CMOS technology that functions from 300 K (room temperature) down to 4.2 K. It has been designed to operate in cryogenic sensor systems as they are cooled from room temperature to their final cryogenic operating temperature. In order to preserve the circuit's performance over this wide temperature range, even in the presence of temperature-induced transistor anomalies, dedicated architecture and switching schemes are employed. SPICE models for adequate circuit simulation at 4.2 K have been extracted. A first prototype of the chosen architecture, an 8-bit ADC in a standard 0.7 mum CMOS technology, achieves a differential nonlinearity (DNL) of 0.5 LSB at room temperature and 1 LSB at 4.2 K at a sampling frequency of 12.5 kHz.
    IEEE Journal of Solid-State Circuits 08/2009; · 3.11 Impact Factor
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    ABSTRACT: New process modules and device architectures for (sub-) 32 nm CMOS lead to both opportunities and challenges for analog/RF and mm-wave circuit design. A survey will be given describing the advanced process modules and competing architectures (planar bulk CMOS versus FinFETS), and their impact on analog/RF performance. FinFETs will be shown to be better suited for analog baseband design and to have acceptable RF performance in the 1-10 GHz range, while planar bulk CMOS outperforms the FinFETs for sub-circuits above 10 GHz.
    Microwave Integrated Circuit Conference, 2008. EuMIC 2008. European; 11/2008
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    ABSTRACT: This paper presents the first standard CMOS flash analog-to-digital converter (ADC) operational over an ultra wide temperature range (UWT) from room temperature (27deg C or 300 K) down to 4 K (-269deg C). To preserve the circuits performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated architecture and switching schemes are employed.
    Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008
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    ABSTRACT: FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are derived to improve the RF performance. For an optimized layout folding, experiments indicate 15% gain in f<sub>T</sub>.
    SOI Conference, 2007 IEEE International; 11/2007
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    ABSTRACT: Inserting a thin metal layer at the Poly-Si/dielectric interface to eliminate gate depletion and boron penetration has recently attracted a considerable attention from the engineering community due to the compatibility of this metal gate stack with conventional poly-Si technology. In this contribution we use CMOS transistors with TiN metal gate of different number of deposition cycles on 2nm SiON gate oxide as a test vehicle to evaluate the work function control and eventual modifications of the interfaces and gate oxide quality. The flexibility in the work function control comes at a cost of degraded performances for lowest deposition cycles corresponding to the band edge work functions.
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    ABSTRACT: A hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates optimal topology combinations using multi-objective evolutionary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combinations of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimental results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed DeltaSigma A/D modulator
    2008 Design, Automation and Test in Europe. 04/2007;
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    ABSTRACT: This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs (I–V, C–V and 1/f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.
    Solid-State Electronics 04/2007; · 1.51 Impact Factor
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    ABSTRACT: A SAR ADC is designed to operate from room temperature down to 4.2K, as needed by cryogenic sensor systems. The ADC is robust to cryogenic temperature-induced transistor anomalies. It has an INL of -0.8 (0.5)LSB and DNL of 1.1 (0.4)LSB at 4.2K(300K). It draws 70muA for a 200pF output capacitor at 3kHz sampling rate and 5V supply
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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    ABSTRACT: This paper presents a continuous-time delta-sigma modulator with a resolution of 10 bits in a 10 MHz signal bandwidth. It is designed in a standard 0.18 mum CMOS technology and consumes 6 mW. A hierarchical bottom-up, multi-objective evolutionary design methodology was developed to reduce design time. It takes advantage of the Pareto-optimal performance solutions of the hierarchically decomposed lower-level sub-blocks to generate the overall Pareto-optimal set at modulator level. A 7-block hierarchical decomposition of a 640-MHz DeltaSigma modulator for 802.11a/b/g WLAN applications is implemented and optimized towards power efficiency.
    Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on; 01/2007
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    ABSTRACT: This paper discusses the realization of an analogue module generator that forms part of a mixed analogue/digital design environment. It is able to design analogue functional modules such as like amplifiers, filters, etc., either in an automatic or in an interactive session, starting from performance specifications over topology selection, parameter optimization and simulation/verification down to lay-out. the analogue module generator is integrated in a commercial EDA framework. Practical design results show the capabilities and efficiency of the system.
    International Journal of Circuit Theory and Applications 12/2006; 23(4):269 - 283. · 1.29 Impact Factor
  • R. Schoofs, M. Steyaert, W. Sansen
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    ABSTRACT: A third-order continuous-time DeltaSigma analog-to-digital converter is designed for the conversion of an input signal bandwidth of 10MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed, low-power building blocks of the modulator. The presented converter achieves a dynamic range of 72dB and a signal-to-noise-and-distortion-ratio of 66dB. The modulator consumes 7.5mW. It is integrated in a 0.18mum standard CMOS technology and occupies an area of 1.65mm<sup>2</sup>
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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    ABSTRACT: Human electrogastric signals can be detected by properly locating electrodes on the abdominal skin. The detailed waveform analysis for medical researches or clinical use is, however, hindered by its poor quality. A modified adaptive enhancing technique is described in the paper for eliminating noise and interference while keeping the modification of the characteristics of the gastric signal component as small as possible. According to the specific properties of the human cutaneous gastric signal the technique used is a two stage adaptive enhancing system of which the first stage is simply an adaptive line enhancer and the last stage is a combination of conventional FIR filering and multichannel adaptive enhancing. The system has been testified by both computer simulations and real measurement processing, and performs well, namely, the noise and disturbance are cancelled and the characteristics of gastric signal component are little affected.
    04/2006: pages 1115-1128;
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    ABSTRACT: A straightforward model and experimental methodology to extract simultaneously the gate capacitance and the gate leakage is presented for ultra thin oxides. Parasitic effects at high frequencies are minimized using a transmission-line approach while a robust extraction algorithm accounts for eventual instrument inaccuracies.
    Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on; 04/2006
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    ABSTRACT: Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (G<sub>m</sub>), provided a degraded voltage gain and a higher leakage current can be tolerated
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    Xiaohong Peng, W. Sansen
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    ABSTRACT: A new performance-boosting frequency compensation technique is presented, named Transconductance with Capacitances Feedback Compensation (TCFC). A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. An optimized TCFC amplifier has been implemented, and fabricated in a 0.35-μm CMOS process. The TCFC amplifier driving a 150-pF load capacitor achieved 2.9-MHz gain-bandwidth product dissipating only 45-μW power with a 1.5 V supply, which shows a significant improvement in MHz·pF/mA performance.
    IEEE Journal of Solid-State Circuits 08/2005; · 3.11 Impact Factor
  • R. Schoofs, M. Steyaert, W. Sansen
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    ABSTRACT: A 1 GHz continuous-time sigma-delta A/D modulator is presented. It is designed in a standard 90 nm CMOS technology. The 1-bit modulator achieves an accuracy of 10 bits in a signal bandwidth of 8 MHz. This paper focuses on the challenges the designer faces when the sampling speed increases and the supply voltage lowers. It is shown that a G<sub>m</sub>C architecture is the most power efficient filter implementation for broadband conversion. Here, the power consumption is determined by thermal noise requirements. Finally, the timing of the feedback pulse is controlled. This ensures an improved stability of the 1 GHz modulator.
    Microwave Symposium Digest, 2005 IEEE MTT-S International; 07/2005
  • Libin Yao, M. Steyaert, W. Sansen
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    ABSTRACT: A low-voltage switched-capacitor fourth-order Σ-Δ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the Σ-Δ loop. These features greatly relax the DC gain and output swing requirements for OTAs in the deep submicron CMOS Σ-Δ modulator. With careful signal scaling, signal swings inside the loop can be suppressed to less than 50% of the reference voltage, which is highly desirable by low-voltage designs. Implemented by a 0.13-μm pure digital CMOS technology, the Σ-Δ modulator achieves 1-MS/s conversion speed and 88-dB DR with 7.4-mW power dissipation under 1.0-V power supply voltage.
    VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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    ABSTRACT: Many analog circuits use matched resistors on chip. The resistors have two components: the resistive elements and the interconnects. The resistive elements have good matching properties. However, the resistance of the interconnects - especially of the contacts and vias - is only guaranteed to be within certain wide limits. If the matched resistors are low-ohmic, then the interconnect dominates the mismatch equations. This is often solved by oversizing the interconnect or by avoiding structures with lots of interconnect. We prefer to characterize these interconnects or even to build resistors using only interconnects. The measurement results show that the interconnect resistance can match as well as poly resistors in the same 0.18 μm technology.
    Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on; 05/2005

Publication Stats

5k Citations
203.31 Total Impact Points


  • 1999–2007
    • imec Belgium
      • Smart Systems and Energy Technology
      Louvain, Flanders, Belgium
  • 1986–2006
    • KU Leuven
      • Department of Electrical Engineering (ESAT)
      Leuven, VLG, Belgium
  • 1998
    • Brno University of Technology
      • Department of Microelectronics
      Brno, South Moravian Region, Czech Republic
  • 1996–1997
    • Università degli Studi dell'Aquila
      Aquila, Abruzzo, Italy
  • 1995
    • AZ Oudenaarde
      Audenaarde, Flanders, Belgium
    • Technische Universiteit Eindhoven
      • Department of Electrical Engineering
      Eindhoven, North Brabant, Netherlands
  • 1994
    • University of Pennsylvania
      • Department of Electrical and Systems Engineering
      Philadelphia, PA, United States
  • 1990
    • Leuven University College
      Louvain, Flanders, Belgium