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ABSTRACT: In this paper, the authors propose a switch-level substrate noise simulation tool named SilcVerify for high-speed memory design based on lightly-doped and nanoscaled CMOS processes. It uses the device switching model (DSM) as its noise source and the adjacent geometry dependent macromodel (AGDM) as its substrate model. The DSM represents the noise injection of each transistor into the substrate. It consists of one current source and one capacitance. The AGDM is a scalable model based on the layout geometry and Voronoi tessellation. Consequently, a sparse network composed with DSMs and AGDMs is solved by using a linear system solution technique. Experimental results for real designs verify that SilcVerify can simulate three orders larger circuits and two orders faster than the reference method using a 3D substrate model and a nonlinear circuit simulator while maintaining the accuracy of about 10% error. SilcVerify can be applied to block placement and guard-ring optimization for PLL jitter reduction
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on; 04/2007
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Hong Yang,
Hyunjae Kim,
Sung-il Park,
Jongseob Kim,
Sung-Hoon Lee,
Jung-Ki Choi,
Duhyun Hwang,
Chulsung Kim,
Mincheol Park,
Keun-Ho Lee,
Young-Kwan Park,
Jai Kwang Shin, Jeong-Taek Kong
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ABSTRACT: The reliability issues, including 100k cycle's endurance and 2 hours high temperature storage (HTS: 150degC, 200degC and 250degC) of sub-90nm NAND flash cells, are studied. Furthermore, the trap generation models in endurance and interface trap recovery model in HTS are proposed. Endurance characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count (DeltaN<sub>it</sub>, DeltaN<sub>ot</sub> infin cycleuarrm). The exponent of interface trap generation both program and erase are 0.62; while in bulk trap generation, the exponent for the cycle count is 0.30, which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide degradation. The HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND flash memory, while stress induced leakage current (SILC) is almost negligible. Thus, based on the reaction-diffusion (R-D) model and Arrhenius approximation, the simplified interface recovery model in HTS is proposed as: dN<sub>it</sub>/N<sub>it</sub> = -k<sub>0</sub> middot exp(-E<sub>a</sub>/k<sub>B</sub>T) middot dt
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on; 11/2006
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Sungpack Hong,
Sungjoo Yoo,
Sheayun Lee,
Sangwoo Lee,
Hye Jeong Nam,
Bum-Seok Yoo,
Jaehyung Hwang,
Donghyun Song,
Janghwan Kim,
Jeongeun Kim,
HoonSang Jin,
Kyu-Myung Choi, Jeong-Taek Kong,
SooKwan Eo
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ABSTRACT: Virtual platform (ViP), or ESL (electronic system level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e. g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.
Hardware/software codesign and system synthesis, 2006. CODES+ISSS '06. Proceedings of the 4th international conference; 11/2006
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ABSTRACT: A multilevel level cell (MLC) technique for flash memories reduces the bit cost and enhances the memory density. However, it is difficult to get a required sensing margin for MLC due to the need for the tight threshold voltage control. We present a unified statistical model which can account for inter-and intra-die variations. The proposed model is implemented into SPICE to predict the distribution of performance. The sensing margin is found to increase by about 30% with optimization of sensitive transistors in the sense amplifier and high voltage regulator. The statistical optimization methodology is essential to achieve an optimal sensing margin and it is widely used for other products such as DRAM, SRAM, DDI and CIS
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on; 04/2006
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ABSTRACT: The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of the system modeling is the modeling of IP components and communication between IPs. To be effective, it is generally accepted that the system modeling should be performed in two steps; In the first step, a fast but some inaccurate system modeling is considered to facilitate the simultaneous development of software and hardware. The second step then refines the models of the software and hardware blocks (i.e., IPs) to increase the simulation accuracy for the system performance analysis. Here, one critical factor required for a successful system modeling is a systematic modeling of the IP blocks and bus subsystem connecting the IPs. In this respect, this work addresses the problem of systematic modeling of the IPs and bus subsystem in different levels of refinements. In the experiments, we found that by applying our proposed IP and bus modeling methods to the MPEG-4 application, we are able to achieve 4/spl times/ performance improvement and at the same time, reduce the software development time by 35%, compared to that by conventional modeling methods.
2008 Design, Automation and Test in Europe. 03/2006; 1:123.
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ABSTRACT: In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design.
Design Automation, 2006. Asia and South Pacific Conference on; 02/2006
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2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA; 01/2006
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Conference Proceeding:
PowerV
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006; 01/2006
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Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006; 01/2006
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ABSTRACT: Electromagnetic interference (EMI) has become more and more important in the electronics systems especially for household appliance. This paper describes a fast and accurate system-level simulation method for the EMI analysis of liquid crystal display (LCD) panel taking into account the operation of full chip level display driver IC (DDI) as an EMI aggressor. Because a LCD panel consists of several PCBs, chips and passive elements, the effort to model the network smaller and the simulation vector shorter is so critical for the analysis to be successful. The modeling aims not only to reduce the network size by considering the operating frequency and switching capability of each component but also to compact the simulation vector in a short period by analyzing the test mode image which has the busiest activity and makes a peak EMI noise level. This method is applied to estimate and suppress EMI noise due to the 8-bit DDI in 40" LCD panel system. As a result, the circuit size of DDI is reduced about 95% and the loss of model accuracy is within 10%. The EMI noise level is decreased by more than 5 dB by finding the optimal point of decoupling capacitor. This method is useful for modeling a large system and analyzing major EMI problem in system-level as well as chip-level.
Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on; 11/2005
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ABSTRACT: In this work, we present the results of three-dimensional CMOS image sensor cell simulation. Electrical characteristics of the device are represented comprehensively. The methodology, describing saturation, charge-voltage conversion, and image lag of a CIS cell in a single simulation analysis, is expected to play a key role in future CMOS image sensor cell development.
Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on; 10/2005
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ABSTRACT: An efficient characterization technique with the spatial correlation matrix from electrical device parameters such as threshold voltage and saturation current accounting for inter- and intra-die variations is demonstrated. Then, a unified statistical model based on the correlation matrix is developed and implemented to the SPICE simulator to predict the distribution of circuit performance. In order to verify our model, test chips which consist of transistors and ring oscillators were fabricated using a 130nm CMOS technology. Simulated delay/skew variations of ring oscillators agree well with the measurement of test chips, maintaining a reasonable accuracy of 85 %. Especially, we show that as the distance of the two ring oscillators becomes larger, the timing skew between them becomes bigger. Moreover, the sensitivity analysis for the performance of simple analog and digital circuit, is performed in terms of inter-and intra-die variation.
Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on; 10/2005
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ABSTRACT: Due to the high speed and low power trends, the power distribution network (PDN) in multilayer printed circuit boards (PCBs) plays a pivotal role in terms of system performance. The paper presents an efficient analysis method for the irregularly shaped power/ground plane pair considering the effect of densely populated power/ground and signal vias in the frequency domain. The plane is divided based on geometric properties and modeled by the parallel-plate transmission line theory. For examination of various via effects, we have modeled vias according to their properties, such as power, ground and signal. Using a conventional circuit simulator, the input- and trans-impedance of power/ground planes are investigated. Since the proposed method is accurate as well as fast, it can be efficiently applied to multilayered PCB structures at the early design stage.
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on; 04/2005
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ABSTRACT: The increase in pattern complexity due to optical proximity correction (OPC), the tight requirements for critical dimension (CD) control and the difficulties in defect inspections make IC manufacture more expensive. To alleviate the high cost, manufacturing requirements must be handled at the design stage to improve the quality and yield of ICs. We demonstrate the extraction of critical areas for detecting failures and a new lithography simulation method for full-chip level optical proximity corrected layout. The methodology has been used in our mask verification process that is called litho-friendly layout (LFL). For the critical area extraction, we present three approaches using process window, normalized image log-slope (NILS) and edge placement error (EPE). For full-chip level simulation, we introduce an automatic calibration method for simulation process parameters, a mask decomposition method and a selective simulation method. The verification process includes lithography process simulation, print-image based LVS (layout vs. schematic) and DRC (design rule check). We also demonstrate that LFL can provide guidelines for better OPC of sub-80 nm processes.
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on; 04/2005
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2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany; 01/2005
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ABSTRACT: The PR(Photoresist) flow process after the development step has been used for patterning of sub-200nm contact holes as the design rule decreases rapidly. To optimize the layout design and process parameters, we develop the new viscous PR flow model which is verified for various PRs by experimental results. Using the model and simulation, we demonstrate the close agreement with VSEM(vertical scanning electron microscope) of the top corner rounding profile of PR and investigate the effect of the dominant variables such as the contact size, surrounding bulk density, and temperature. This model is also integrated with lithography simulator. The layout design and process condition of patterns with various contact sizes are optimized by using our new methodology. The viscous flow model linked to the lithography simulator can be effectively used in predicting the contact patterning process and optimizing the layout as well as analyzing defects.© (2004) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
05/2004;
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ABSTRACT: For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings; 03/2004
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ABSTRACT: In the trends of high density high speed and low power consumption, the analysis of power distribution networks is rapidly becoming an essential step in the design of high performance ICs. Nevertheless, the analysis is a great challenge, due to the large size of the networks. In this paper, we propose a variable reduction technique for the analysis of large-scale power distribution networks. The basic procedure of the proposed technique is reducing the power distribution network to a manageable size, solving the equation of the reduced network and then recovering the solutions of the original network. With the proposed variable reduction technique, we have achieved speed improvements up to several tens of times compared to the high performance linear system solution techniques, with no loss of accuracy.
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on; 02/2004
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ABSTRACT: Due to the increase of portable and high performance integrated circuit (IC) applications, package designs get smaller and more complex. Chip scaled multi-layer IC packages become one of the solutions to accommodate such requirements. In the design environment for complicated packages, a fast and accurate interconnect parasitic extraction method is very important in order to explore alternative designs in a limited time and to cope with lacking of design margins. This paper proposes a novel interconnect parasitic extraction method which combines the advantages of the inherently fast 2D approach and accurate 3D approach. Thus, it efficiently models the 3D effects around traces and vias such as the variable shaped reference plane and shielding, chip placement, package fringes, and current flows. The speed and the accuracy of parasitic, extractions are substantially improved compared to the conventional method in the application of multi-layer packages for leading edge memory products.
Electrical Performance of Electronic Packaging, 2003; 11/2003
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ABSTRACT: In this paper, we propose a new fast and practical technique to eliminate known false paths during static timing analysis (STA). False paths are verified fast using additional information stored in arrival times, which is a pass-through history of exceptional nodes. The information can be constructed with small memory overhead because an individual false path list is not managed at each arrival time. We adapted this method to classical arrival time computation and a critical path searching algorithm. The feature is used in CubicTime, our full-chip gate level static timing analyzer, supporting multiple clock domains. We describe the details of our algorithm and the experimental results compared to those of our previous method and a de-facto industry-standard STA tool.
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]; 10/2003
