Hayder Mrabet

Pierre and Marie Curie University - Paris 6, Lutetia Parisorum, Île-de-France, France

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Publications (22)0 Total impact

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    ABSTRACT: The Wave Dynamic Differential Logic (WDDL) is a promising countermeasure to protect cryptographic devices from Differential Power Attacks (DPA). But the key challenge is to maintain symmetry between dual networks, so as to obtain equal propagation delays and power consumption on differential signals. In this paper, we deal with the problem of timing unbalance. We study the impact of different placement strategies on the delay unbalance in a Tree-based FPGA. In addition, we present a new timing-balance driven router which is based on the Pathfinder routing algorithm. Our placement and routing tools improve significantly the delay balance. In fact, the results obtained with WDDL DES netlist show that the average delay unbalance was reduced by 90%.
    16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunesia, 13-19 December, 2009; 01/2009
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    ABSTRACT: In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in wave dynamic differential logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing techniques reduce the delay unbalance significantly. They achieve 93% of average timing balancing improvement in WDDL designs.
    ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings; 01/2009
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    ABSTRACT: In this paper we present a new mesh of tree FPGA architecture, where clusters are surrounded by a mesh style interconnect and each cluster local interconnect is equivalent to a depopulated tree-based topology. The particularity of the architecture allows to retain the distinction between mesh and tree levels in the mapping phase. This has an important impact on run time saving and tool simplification. Nevertheless an efficient interconnect distribution must be found between both levels, to reach a tradeoff between interconnect reduction and routability. With the proposed Mesh of Tree architecture, we divided the required run time by 3 and reduced the routing interconnect by 24%, compared to the clustered VPR-style mesh architecture.
    Field-Programmable Technology, 2007. ICFPT 2007. International Conference on; 01/2008
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    ABSTRACT: In this paper we present the effect of lookup table (LUT)size (no of inputs to a LUT) and cluster size (no of LUTs per cluster) on the area and critical path of a tree based FPGA architecture (MFPGA). For this purpose we have designed a flow that places and routes a set of bench mark circuits on different tree based architectures with varying lookup table (lookup table size varies from 3 to 7) and cluster sizes ( cluster size varies from 4 to 8). With the help of experimental results we have analyzed the alteration in the MFPGA area with different LUT and cluster sizes. We have shown that in general LUTs having 4 or 5 inputs and clusters having 4 or 5 LUTs per cluster produce most efficient results in terms of area for the tree based architecture. We have also determined the mutation in the number of switches crossed by the critical path with changing LUT and cluster size and we have shown that architectures with higher LUT size and higher cluster size can be more optimal in terms of critical path though they are not optimal in terms of area.
    ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings; 01/2008
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    ABSTRACT: This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results show that the Tree-based architecture can implement MCNC benchmark circuits with an average gain of 54% in total area compared with Mesh architecture.
    Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008; 01/2008
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    H. Parvez, H. Mrabet, H. Mehrez
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    ABSTRACT: This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of Single Event Upsets (SEU). The FPGA layout is generated using a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated to 130 nm technology.
    Research in Microelectronics and Electronics, 2008. PRIME 2008. Ph.D.; 01/2008
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    ABSTRACT: This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of single event upsets (SEU). The FPGA layout is generated in a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated and taped out in 130 nm technology.
    01/2008;
  • Zied Marrakchi, Hayder Mrabet, Habib Mehrez
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    ABSTRACT: This paper presents an improved cluster-based Mesh architecture called Mesh of Tree. The intra-cluster interconnect has an optimized Tree topology allowing to connect external signals and local feedbacks to logic blocks inputs. Unlike the well known VPR cluster-based Mesh architecture, the depopulated local interconnect allows to consider sizeable clusters. Moreover density is improved and interconnect switches requirement is reduced by 42% compared to the VPR-based architecture.
    01/2008;
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    ABSTRACT: In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network. Unlike previous clustered mesh architectures, the mesh of tree allows us to consider large clusters sizes (thanks to MFPGA depopulated local interconnect). Experimentation shows that we obtain a reduction of 14% in switches number and 2 times in the placement and routing run time. Furthermore, compared to MFPGA, the mesh of tree achieves full routability of all MCNC benchmarks since we can easily control both clusters LUTs occupation and mesh channel width.
    Architecture of Computing Systems (ARCS), 2007 20th International Conference on; 04/2007
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    ABSTRACT: In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is imple- mented as an MFPGA tree network (6). Unlike previous clustered mesh architectures, the mesh of tree allows us to consider large clusters sizes (thanks to MFPGA depopu- lated local interconnect). Experimentation shows that we obtain a reduction of 14% in switches number and 2 times in the placement and routing run time. Furthermore, com- pared to MFPGA, the mesh of tree achieves full routability of all MCNC benchmarks since we can easily control both clusters LUTs occupation and mesh channel width.
    First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings; 01/2007
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    Z. Marrakchi, H. Mrabet, H. Mehrez
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    ABSTRACT: In this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed
    Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on; 10/2006
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    ABSTRACT: Integrating an embedded FPGA into SoC allows post-fabrication changes. Thanks to their unlimited reconfigurability, eFPGAs are able to implement specific functions, thus improves the systems performance. In this paper the authors present an SRAM-based eFPGA architecture. The authors explore the hardware aspects of the eFPGA including internal structure and external coupling with a VCI interconnect. The authors also focus on the design flow for the implementation and the configuration
    Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on; 10/2006
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    Z. Marrakchi, H. Mrabet, H. Mehrez
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    ABSTRACT: In this paper we evaluate a new multilevel hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks. A downward network based on the butterfly-fat-tree topology, and a special rising network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller area.
    Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on; 04/2006
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    ABSTRACT: This paper presents a new multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: a predictible downward network based on the Butterfly-Fat-Tree topology, and an upward network using hierarchy. Studies based on the Rent's Rule show that wiring and switch requirements in the MFPGA grow slower than in traditional topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results based on the MCNC benchmarks show that MFPGA can implement circuits with an average gain of 40% in total area compared with mesh architecture
    2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA; 01/2006
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    Z. Marrakchi, H. Mrabet, H. Mehrez
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    ABSTRACT: The complexity of circuits to implement on FPGA has necessitated to explore hierarchical interconnect architectures. A large body of work shows that a good partitioning hierarchy, as measured by the associated rent parameter, will correspond to an area-efficient layout. We define the architecture rent parameter of a netlist to be the lowest bound on the rent parameter of any partitioning hierarchy of the netlist. Experimental results show that a combination between a multilevel bottom-up clustering and a top-down refinement generates partitioning hierarchies whose rent parameters are lower than those of other methods
    Research in Microelectronics and Electronics 2006, Ph. D.; 01/2006
  • Zied Marrakchi, Hayder Mrabet, Habib Mehrez
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    ABSTRACT: In this paper we evaluate a new multi-level hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology and a special hierarchical upward network. The Downward network uses linear populated and unidirectional Switch Boxes (SBs) and gives one path from each wire-source in the top to reach a leaf (Logic Block: LB) in the lowest level. The upward network connects the LBs output and the input Pads to the SBs situated in different levels of the downward network. New tools are developed to program the new architecture. The global placement approach uses a combination of clustering and partitioning with adaptations to deal with the multi-level interconnect topology. First we run a multi-level bottom-up clustering to reduce external connections. Second we run a multi-level top-down refinement to reduce signals bandwidth of clusters in each level. A detailed placer defines the position of each LB inside a cluster and considers more complex routing constraints. The router is an adaptation of Pathfinder. The global routing consists on selecting the level to use. Signals routing is immediate since path to reach a destination is predictable and unique. Results are based on the MCNC benchmarks and they quantify the LB occupancy and routability. Comparison with the traditional symmetric Manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller total area.
    Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006; 01/2006
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    Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006; 01/2006
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    ABSTRACT: Creation of large FPGAs needs radical efficient changes in architecture to improve speed, density and software mapping time. Based on industry experience with standard ASICs, we believe that partitioning and hierarchy become an obligation for FPGA hardware and software developments. As an alternative we propose a new Multilevel hierarchical FPGA (MFPGA) architecture where logic blocks and routing resources are sparsely partitioned into multilevel clustered structure. Since the routing resources consume most of the FPGA area, we focus on interconnect check. We try to achieve the best area efficiency by balancing interconnect and logic block utilization. The proposed MFPGA interconnect unifies two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology, and an upward network that uses hierarchy. The Downward network uses linear populated and unidirectional switch boxes and gives one path from each wire-source in the top to each leaf (logic block) in the lowest level. The upward network connects the logic blocks outputs and the input pads to the different levels of the downward network. Studies based on the Rent's Rule show that wiring and switch requirements in the MFPGA grow slower than in traditional topologies. We used MCNC benchmark circuits to compare the switch and area requirements between our MFPGA architecture and the traditional mesh topology. New software tools for placement and routing were developed to conduct this study on the MFPGA architecture. Expermimental results show that MFPGA can implement circuits with fewer switches and a smaller total area than mesh architecture.
    Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006; 01/2006
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    Z. Marrakchi, H. Mrabet, H. Mehrez
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    ABSTRACT: We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power dissipation is reduced by an average of 8.5%
    Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on; 10/2005
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    Z. Marrakchi, H. Mrabet, H. Mehrez
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    ABSTRACT: In this paper we present a new clustering technique, based on the multilevel partitioning, for hierarchical FPGAs. The purpose of this technique is to reduce area and power by considering routability in early steps of the CAD flow. We show that this technique can reduce the needed tracks in the routing step by 15% compared with the other packing tools.
    Research in Microelectronics and Electronics, 2005 PhD; 08/2005