-
[show abstract]
[hide abstract]
ABSTRACT: Forward body biasing is a promising approach for realizing optimum threshold-voltage ( V <sub>TH</sub>) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias ( VF ) decreases the depletion width ( X <sub>DEP</sub>) in the channel region, it reduces V <sub>TH</sub> rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small X <sub>DEP</sub> ) at low V <sub>TH</sub> notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for | VF | should be set at 0.6-0.7 V, which is sufficient to realize significant advantages of forward body biasing.
IEEE Transactions on Electron Devices 11/2008; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. It was also found that the gate leakage current and 1/f noise in (110) samples were sensitive to off-axis angle.
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on; 07/2007
-
A. Kaneko,
A. Yagishita,
K. Yahashi,
T. Kubota,
M. Omura,
K. Matsuo,
I. Mizushima,
K. Okano,
H. Kawasaki,
T. Izumida, [......],
N. Aoki,
A. Kinoshita,
J. Koga,
S. Inaba,
K. Ishimaru,
Y. Toyoshima, H. Ishiuchi,
K. Suguro,
K. Eguchi,
Y. Tsunashima
[show abstract]
[hide abstract]
ABSTRACT: High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with L<sub>g</sub> = 15 nm and W<sub>fin</sub> =15 nm at V<sub>d</sub>= 1.0 V and I<sub>off</sub>= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
-
T. Kanemura,
T. Izumida,
N. Aoki,
M. Kondo,
S. Ito,
T. Enda,
K. Okano,
H. Kawasaki,
A. Yagishita,
A. Kaneko,
S. Inaba,
M. Nakamura,
K. Ishimaru,
K. Suguro,
K. Eguchi, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: We discussed the optimization of structure and doping profile of bulk-FinFETs by using 3D process and device simulations. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. The analysis of stress field for bulk-FinFETs and SOI-FinFETs revealed that the channel stress induced by a stress liner (SL) in the bulk-FinFET is larger than that for the SOI-FinFET. In addition, we applied a raised source/drain (RSD) structure to the bulk-FinFETs and optimized doping profile in the RSD region. The combination of stress liner and RSD structure is found to be efficient for improving drive current of a bulk-FinFET
Simulation of Semiconductor Processes and Devices, 2006 International Conference on; 10/2006
-
S. Inaba,
K. Okano,
T. Izumida,
A. Kaneko,
H. Kawasaki,
A. Yagishita,
T. Kanemura,
T. Ishida,
N. Aoki,
K. Ishimaru,
K. Suguro,
K. Eguchi,
Y. Tsunashima,
Y. Toyoshima, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: This paper discusses the possibility of future large scale integration (LSI) of multi-gate device. FinFET is thought to he the most promising multi-gate device for LSI, because it easily realizes the self-aligned double-gate structure. At first, the feasibility of SRAM operation with FinFET in hp22 nm node is studied by simulation in terms of V<sub>t</sub> fluctuation control. Next, it is demonstrated that FinFET on bulk Si substrate (bulk-FinFET) is a suitable candidate for cost-effective LSI manufacturing. The integration schemes of FinFET and planar FET on the same substrate are also developed for the fabrication of 128 Kbit SRAM ADM (array diagnostic monitor). Finally, successful SRAM cell operation is demonstrated with FinFET of L<sub>g</sub> = 20 nm. Therefore, FinFET integrated circuit can provide a unique solution for future low-power SoC
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European; 10/2006
-
[show abstract]
[hide abstract]
ABSTRACT: Active threshold voltage V<sub>TH</sub> control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impact of substrate bias V<sub>SUB</sub> on hot-carrier reliability is presented. The impact varies with the gate length and body effect factor. These findings are explained, and the effects of future scaling are discussed using a quasi-two-dimensional model. Significant and important improvement in hot-carrier lifetime with forward-bias V<sub>SUB</sub> can be expected for deeply scaled CMOS devices, making it an attractive method for extending the scalability of bulk-Si transistor technology.
IEEE Electron Device Letters 08/2006; · 2.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: An RF MEMS variable capacitor using hybrid actuation of piezoelectric and electrostatic forces is presented. A surface micromachining process is used to fabricate the device. The piezoelectric actuator, which uses thin film PZT, enables low voltage actuation while the electrostatic actuator realizes large capacitance ratio. The measured capacitance ratio is Cmax/Cmin=14 at 5V. We demonstrate that the hybrid actuation enables to lower the pull-in voltage without changing the pull-out voltage. We also show that the shift of pull-out voltage due to dielectric charging can be reduced drastically at actuation voltages below 10V. In this sense, the hybrid actuation can realize low voltage operation with enhanced robustness for stiction
Microwave Symposium Digest, 2006. IEEE MTT-S International; 07/2006
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (τ<sub>pd</sub>) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same V<sub>dd</sub>. It is also confirmed that about 30% better power-delay product can be realized at the same τ<sub>pd</sub> with reduced V<sub>dd</sub> in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of ∼95 mV at V<sub>dd</sub>=0.6 V. Smaller bitline delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for α-particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for low-power system-on-a-chip (SoC).
IEEE Journal of Solid-State Circuits 07/2006; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body bias is experimentally evaluated for devices with various channel-doping profiles to provide guidance for channel engineering in a forward body-biasing scheme. Furthermore, simulations of 10-nm-gate CMOS (hp22-nm node) devices are performed to study the optimal channel-doping profile and gate work function engineering for a forward biasing scheme.
IEEE Electron Device Letters 06/2006; · 2.85 Impact Factor
-
K. Okano,
T. Izumida,
H. Kawasaki,
A. Kaneko,
A. Yagishita,
T. Kanemura,
M. Kondo,
S. Ito,
N. Aoki,
K. Miyano, [......],
K. Iwade,
T. Kubota,
T. Matsushita,
I. Mizushima,
S. Inaba,
K. Ishimaru,
K. Suguro,
K. Eguchi,
Y. Tsunashima, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
-
A. Kaneko,
A. Yagishita,
K. Yahashi,
T. Kubota,
M. Omura,
K. Matsuo,
I. Mizushima,
K. Okano,
H. Kawasaki,
S. Inaba,
T. Izumida,
T. Kanemura,
N. Aoki,
K. Ishimaru, H. Ishiuchi,
K. Suguro,
K. Eguchi,
Y. Tsunashima
[show abstract]
[hide abstract]
ABSTRACT: We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
-
M. Fujiwara,
T. Morooka,
N. Yasutake,
K. Ohuchi,
N. Aoki,
H. Tanimoto,
M. Kondo,
K. Miyano,
S. Inaba,
K. Ishimaru, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T<sub>BOX</sub> is varied from 5 nm to 145 nm. In addition, optimum design regions of T<sub>BOX</sub> for achieving performance requirements are demonstrated.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
-
K. Adachi,
K. Ohuchi,
N. Aoki,
H. Tsujii,
T. Ito,
H. Itokawa,
K. Matsuo,
K. Suguro,
Y. Honguh,
N. Tamaoki,
K. Ishimaru, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs performance viewpoint. We reported that LSA is the leading candidate for 45 nm node and beyond.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
-
[show abstract]
[hide abstract]
ABSTRACT: HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S<sub>vg</sub> with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S<sub>vg</sub>) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 × 10<sup>17</sup> cm<sup>-3</sup>eV<sup>-1</sup>. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
-
[show abstract]
[hide abstract]
ABSTRACT: We fabricated MOSFET devices using flash lamp annealing (FLA), and studied the halo profile dependence on CMOSFETs performance. Although FLA is high temperature anneal of 1000°C or more and has soaking time corresponding to millisecond, it causes anomalous low level of halo dopant activation and redistribution. This anomaly degrades threshold voltage roll-off characteristics and Ion-Ioff characteristics. In this paper, we investigated halo dopant redistribution at each process step and the halo condition dependence of CMOSFETs characteristics, and proposed the design guideline of halo condition using FLA.
Junction Technology, 2005. Extended Abstracts of the Fifth International Workshop on; 07/2005
-
H. Kawasaki,
K. Ohuchi,
A. Oishi,
O. Fujii,
H. Tsujii,
T. Ishida,
K. Kasai,
Y. Okayama,
K. Kojima,
K. Adachi,
N. Aoki,
T. Kanemura,
D. Hagishima,
M. Fujiwara,
S. Inaba,
K. Ishimaru,
N. Nagashima, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: This paper discusses the root causes of the fact that only slight performance improvement of MOSFET with strained-Si substrate has been achieved in short channel region (L < 100 nm). The performance improvement in short channel region is found to deteriorate mainly due to the parasitic resistance increase and tensile stress relaxation in the strained-Si layer. In regard to the parasitic resistance and the stress relaxation in small device geometry, the scaling impacts of strained-Si layer thickness (T<sub>ss</sub>) are investigated from the viewpoint of both DC and AC characteristics. Within this work, T<sub>ss</sub> reduction down to 5 nm improves the current drive (I<sub>d</sub>) of nFET up to 6 % (L < 50 nm) compared with conventional bulk nFET. Propagation delay time (τ<sub>pd</sub>) improvement in CMOS inverter is also observed to be more than 15 %. Finally, the impurity profile optimization is proposed to improve MOSFET performance toward the 45 nm node CMOS era.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
[show abstract]
[hide abstract]
ABSTRACT: 65 nm gate length HfSiON-CMOSFET was fabricated with various Hf concentrations and gate spacers in view of device performance and reliability. The negative charges are generated in HfSiON/Si-substrate interface at the gate edge region for HfSiON with high Hf concentration. SiN offset spacer suppresses the charge generation and the degradation of drive current. Even so, HfSiON with low Hf concentration is higher at performance and reliability than that with high one. Moreover, the optimized HfSiON shows scalability of up to hp45 nm low standby power (LSTP).
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
S. Inaba,
K. Miyano,
H. Nagano,
A. Hokazono,
K. Ohuchi,
I. Mizushima,
H. Oyamatsu,
Y. Tsunashima,
K. Ishimaru,
Y. Toyoshima, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C<sub>j</sub>) has been reduced in SODEL FET, i.e., C<sub>j</sub> (area) was ∼0.73 fF/μm<sup>2</sup> both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient γ is also reduced to less than 0.02 V<sup>1</sup>2/. Nevertheless, current drives of 886 μA/μm (I<sub>off</sub>=15 nA/μm) in nFET and -320 μA/μm (I<sub>off</sub>=10 nA/μm) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V<sub>dd</sub>|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.
IEEE Transactions on Electron Devices 10/2004; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we describe the high analog performance of MOSFETs and inductors on 1.7μm ultra-thin chip with permalloy film.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
-
N. Yasutake,
K. Ohuchi,
M. Fujiwara,
K. Adachi,
A. Hokazono,
K. Kojima,
N. Aoki,
H. Suto,
T. Watanabe,
T. Morooka, [......],
M. Ohmura,
K. Miyano,
H. Yamada,
H. Tomita,
D. Matsushita,
K. Muraoka,
S. Inaba,
M. Takayanagi,
K. Ishimaru, H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V<sub>dd</sub> condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f<sub>i</sub> is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
