[Show abstract][Hide abstract] ABSTRACT: In this paper, we have fabricated and investigated the AlGaN/GaN fin-shaped field-effect transistors (FinFETs) with and without TMAH surface treatment. DC and noise characteristics of the FinFETs were compared to evaluate the interface quality between Al2O3 layer and the side-wall GaN surface. The tetramethyl ammonium hydroxide (TMAH)-treated device with a fin width of 70 nm and gate length, Lg = 5 μm exhibited excellent device performances, such as drain current of 0.16 mA and transconductance (gm) of 0.11 ms, both 30% improved, and extremely small gate leakage current of about 10−9 A at Vgs = −5 V which is approximately two orders lower in magnitude compared to that of the device without TMAH treatment. Improved low-frequency noise performances were obtained for TMAH treated device due to the enhanced side-wall quality after the TMAH surface treatment. The trap density was found to be reduced approximately one order after TMAH treatment. Thus, simple surface treatment not only smoothens the sidewall surface but also eliminates the plasma damage caused during the fin etching, which leads to the reduction of trap density in AlGaN/GaN FinFETs.
[Show abstract][Hide abstract] ABSTRACT: AlGaN/GaN FinFETs with various fin widths (Wfin), which have both a 2DEG channel and two sidewall MOS channels, have been fabricated by using electron-beam lithography and subsequent sidewall wet etch in tetramethyl ammonium hydroxide (TMAH) solution. The devices with wide Wfin of 150 nm showed normally-on operation with threshold voltage (Vth) of −2.5 and −5.0 V, respectively. The devices also exhibited broad transconductance (gm), and excellent off-state performance with very low subthreshold swing (SS). On the other hand, narrow device with Wfin of 50 nm exhibited normally-off operation with Vth of 3.0 V, but degraded SS due to trapping effect at the sidewall of fin.
[Show abstract][Hide abstract] ABSTRACT: We investigated the characteristics of state-of-the-art FDSOI MOSFETs in a wide range of temperature by focusing on the effects of the back-gate bias, Si film thickness and channel length. High device performance and remarkably reduced short-channel effect with decreasing Si film thickness are achieved in ultra-thin film SOI devices. Systematic measurements reveal an unusual coupling effect resulting from the competition between front-gate, back-gate and temperature-dependent short-channel effect. Counter-intuitively, the impact of the back-gate bias can be smaller in 5 nm than in 10 nm thick MOSFETs, in particular in very short devices operated at 300 K.
[Show abstract][Hide abstract] ABSTRACT: Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split – measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the response of the channel in regular, large-area ones, making the extraction in standard samples problematic.
IEEE Transactions on Electron Devices 09/2015; 62(9):2717-2723. DOI:10.1109/TED.2015.2454438 · 2.47 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: AlGaN/GaN FinFETs with and without TMAH surface treatment have been fabricated, DC and noise characteristics were compared to verify the surface improvement. Higher DC performances and lower noise performances were obtained for TMAH treated device due to improved side-wall surface after the surface treatment.
Insulating Films on Semiconductors 2015, Udine, Italy; 06/2015
[Show abstract][Hide abstract] ABSTRACT: Multi-carrier transport in planar fully-depleted silicon-on-insulator (FD-SOI) MOSFETs has been investigated employing magnetic-field dependent geometrical magnetoresistance measurements and high-resolution mobility spectrum analysis. The results indicate that electronic transport in the 10 nm thick Si channel layer is due to two distinct and well-defined electron species. Although self-consistent Schrödinger–Poisson numerical calculations indicate significant localization of the total electron population near the back and front interfaces, the results of mobility spectrum analysis suggest that the mobility distributions associated with these spatially localized populations are strongly coupled through carrier scattering processes, and do not have independent and distinguishable mobility distributions. The two detected electron mobility distributions are thus evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs. The mobility maximum of the dominant carrier was found to occur under gate bias conditions that result in a minimum perpendicular effective electric field.
[Show abstract][Hide abstract] ABSTRACT: The Hot Carrier (HC) reliability of NMOS transistors fabricated on biaxially tensile-strain SOI substrates (sSOI) is compared to that of devices fabricated on standard unstrained SOI substrates. It is shown that sSOI-based devices not only exhibit a 10% higher performance in term of ION/IOFF but also show superior HC reliability at same drive current. This reliability improvement may be explained by a better interface quality for sSOI films.
[Show abstract][Hide abstract] ABSTRACT: An AlGaN/GaN-based Ω-shaped nanowire fin-shaped FET (FinFET) with a fin width of 50 nm was fabricated using tetramethylammonium hydroxide (TMAH)-based lateral wet etching. An atomic layer deposited (ALD) HfO2 side-wall layer served as the etching mask. ALD Al2O3 and TiN layers were used as the gate dielectric and gate metal, respectively. The Ω-shaped gate structure fully depletes the active fin body and almost completely separates the depleted fin from the underlying thick GaN buffer layer, resulting in superior device performance. The top-down processing proposed in this work provides a viable pathway towards gate-all-around devices for III-nitride semiconductors.
[Show abstract][Hide abstract] ABSTRACT: Several types of floating-body capacitorless 1T-DRAM memory cells with planar SOI or multi-gate configuration are reviewed and compared. We show that 1T-DRAMs are also compatible with the 'unified memory' paradigm which aims at combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We focus on our recently proposed concepts (MSDRAM, A2RAM and Z2-FET), by addressing the device architecture and fabrication, operating mechanisms, and scaling issues. Experimental results together with numerical simulations indicate the directions for performance optimization.
[Show abstract][Hide abstract] ABSTRACT: The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5–10 nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond VD > 1.0 V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations.
[Show abstract][Hide abstract] ABSTRACT: Multicarrier transport planar fully-depleted silicon-on-insulator MOSFETs has been investigated employing magnetic-field dependent geometrical magnetoresistance measurements and high-resolution mobility spectrum analysis. The results indicate that electronic transport in the 10 nm thick Si channel layer is due to two distinct and well-defined electron species. According to self-consistent Poisson-Schrödinger calculations, the two distinct electron species detected correspond to carriers in distinct energy sub-bands arising from strong carrier confinement and volume inversion. The mobility peak of the dominant carrier was found to occur under gate bias conditions that result in a minimum perpendicular effective electric field.
[Show abstract][Hide abstract] ABSTRACT: We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the need to compare the long and short devices. The proposed method is validated by experimental data and numerical simulations.
[Show abstract][Hide abstract] ABSTRACT: A2RAM prototype devices have been demonstrated in both SOI and bulk technologies. The fabrication process has successfully achieved the characteristic retrograde doping profile of the channel which allows the coexistence of electrons and holes in the same body while maintaining low-voltage single-gate operation. The different prototypes have been electrically characterized, all of them exhibiting memory effect. The SOI samples present the best performance, showing very attractive current margin between states, competitive retention time, reasonable variability, immunity to disturbance events and no endurance issues even in the short-channel devices fabricated in the most advanced 22 nm process.
[Show abstract][Hide abstract] ABSTRACT: Tunneling-based transistors (TFETs) have attracted interest due to their (theoretical) capability of switching more sharply than MOSFETs. However, other mechanisms that take place in SOI devices can provide even more abrupt switching and higher current. We examine the family of emerging TFET-competing devices based on barrier modulation, bipolar amplification and impact ionization. Practical results for devices fabricated in 14-28 nm FDSOI technology will be discussed.