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C. Xu,
P. Batude,
M. Vinet,
M. Mouis,
M. Casse,
B. Sklenard,
B. Colombeau,
Q. Rafhay,
C. Tabone,
J. Berthoz, [......], A. Toffoli,
R. Kies,
C. Le Royer,
S. Morvan,
A. Pouydebasque,
X. Garros,
A. Pakfar,
C. Tavernier,
O. Faynot,
T. Poiroux
[show abstract]
[hide abstract]
ABSTRACT: For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (> 1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.
2012 International Symposium on VLSI Technology, Systems and Applications (2012 VLSI-TSA); 04/2012
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Microelectronic Test Structures (ICMTS), 2012 IEEE International Conference on; 03/2012
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B. Sklenard,
C. Xu,
P. Batude,
B. Previtali,
C. Tabone,
Q. Rafhay,
B. Colombeau,
F. -A Khaja,
I. Martin-Bragado,
J. Berthoz,
F. Allain, A. Toffoli,
R. Kies,
M. -A Jaud,
P. Rivallin,
S. Cristoloveanu,
C. Tavernier,
O. Faynot,
T. Poiroux
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.
Ultimate Integration on Silicon (ULIS); 03/2012
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N Pashkov,
G Navarro,
J-C Bastien,
M Suri,
L Perniola,
V Sousa,
S Maitrejean,
A Persico,
A Roule, A Toffoli,
G Reimbold,
B De Salvo,
O Faynot,
P Zuliani,
R Annunziata
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European; 09/2011
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J. Mazurier,
O. Weber,
F. Andrieu, A. Toffoli,
O. Rozeau,
T. Poiroux,
F. Allain,
P. Perreau,
C. Fenouillet-Beranger,
O. Thomas,
M. Belleville,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: In this paper, an in-depth variability analysis, i.e., from the threshold voltage V<sub>T</sub> of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local V<sub>T</sub> variability σ(V)<sub>T</sub> lower than A(V)<sub>T</sub> = 1.4 mV · μm is demonstrated. We investigated how this good V<sub>T</sub> variability is reported on the SNM fluctuations σ<sub>SNM</sub> at the SRAM circuit level. It is found experimentally that σ<sub>SNM</sub> is correlated directly to the σ(V)<sub>T</sub> of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The V<sub>T</sub> variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V)<sub>T</sub> in drive nMOSFETs is the key parameter to control for minimizing σ<sub>SNM</sub>.
IEEE Transactions on Electron Devices 09/2011; · 2.32 Impact Factor
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G Navarro,
N Pashkov,
M Suri,
P Zuliani,
R Annunziata,
V Sousa,
L Perniola,
S Maitrejean,
A Persico,
A Roule, A Toffoli,
B De Salvo
Memory Workshop (IMW), 2011 3rd IEEE International; 05/2011
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A. Fantini,
V. Sousa,
L. Perniola,
E. Gourvest,
J.C. Bastien,
S. Maitrejean,
S. Braga,
N. Pashkov,
A. Bastard,
B. Hyot, [......],
F. Fillot,
F. Pierre,
R. Annunziata,
D. Benshael,
P. Mazoyer,
C. Vallée,
T. Billon,
J. Hazart,
B. De Salvo,
F. Boulanger
[show abstract]
[hide abstract]
ABSTRACT: The commercialization of Phase-Change Memories (PCM), based on the well-known GST compound, have been recently started, tailored for consumer applications. Despite other excellent performances (i.e. low-power, scalability,...), data retention is assured up to 85°C, still limited for the automotive market segment. Alternative active material able to comply with the stringent requirements of automotive applications should possibly exhibit higher crystallization temperature (T<sub>C</sub>) as well as higher Activation Energy (E<sub>A</sub>) with respect to GST. Recent literature shows that GeTe provides better retention, while several works put in evidence how data retention is enhanced by inclusions in pure host alloys.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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V Sousa,
L Perniola,
G Navarro,
N Pashkov,
M Suri,
A Persico,
E Henaff,
F Fillot,
F Pierre,
A Roule, [......],
D Blachier,
A Bastard,
JC Bastien,
B Hyot,
B André,
G Reimbold,
B De Salvo,
O Faynot,
P Zuliani,
R Annunziata
EPCOS; 01/2011
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G.B. Beneventi,
L. Perniola,
A. Fantini,
D. Blachier, A. Toffoli,
E. Gourvest,
S. Maitrejean,
V. Sousa,
C. Jahan,
J.F. Nodin, [......],
H. Feldis,
G. Reimbold,
T. Billon,
B. De Salvo,
L. Larcher,
P. Pavan,
D. Bensahel,
P. Mazoyer,
R. Annunziata,
F. Boulanger
[show abstract]
[hide abstract]
ABSTRACT: In this paper we present a study of Phase-Change non-volatile Memory (PCM) devices integrating carbon-doped GeTe as chalcogenide material. Carbon-doped GeTe, named GeTeC, remarkably lowers the RESET current and features very good data retention properties as well. In particular, GeTe PCM with 10% carbon inclusions (named GeTeC10%) yields about 30% of RESET current reduction with respect to pure GeTe and GST. Furthermore, our GeTeC10% memory cells are expected to guarantee a 10-years-lifetime-temperature of about 127°C, which is one of the highest ever reported for PCM. The outstanding properties of GeTeC make this material promising for non-volatile memory technologies.
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European; 10/2010
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M.-A. Jaud,
P. Scheiblin,
S. Martinie,
M. Cassé,
O. Rozeau,
J. Dura,
J. Mazurier, A. Toffoli,
O. Thomas,
F. Andrieu,
O. Weber
[show abstract]
[hide abstract]
ABSTRACT: We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data on both mobility and electrical figures of merit (device and SRAM) offers major opportunities for predictive design based on TCAD simulations.
Simulation of Semiconductor Processes and Devices (SISPAD), 2010 International Conference on; 10/2010
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F. Andrieu,
O. Weber,
J. Mazurier,
O. Thomas,
J.-P. Noel,
C. Fenouillet-Béranger,
J.-P. Mazellier,
P. Perreau,
T. Poiroux,
Y. Morand, [......],
P. Gaud,
V. Paruchuri,
K.K. Bourdelle,
W. Schwarzenbach,
O. Bonnin,
B.-Y. Nguyen,
B. Doris,
F. Bœuf,
T. Skotnicki,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<sub>T</sub>-variability performances are obtained (A<sub>VT</sub>=1.45mV.μm). This leads to 6T-SRAM cells with good characteristics down to V<sub>DD</sub>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<sub>SNM</sub><;SNM/6) down to V<sub>DD</sub>=0.7V. We also demonstrate ultra-low leakage (<;0.5pA/μm) on UT2B devices at L<sub>G</sub>=30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).
VLSI Technology (VLSIT), 2010 Symposium on; 07/2010
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G.B. Beneventi,
E. Gourvest,
A. Fantini,
L. Perniola,
V. Sousa,
S. Maitrejean,
J.C. Bastien,
A. Bastard,
A. Fargeix,
B. Hyot, [......],
H. Feldis,
G. Reimbold,
T. Billon,
B. De Salvo,
L. Larcher,
P. Pavan,
D. Bensahel,
P. Mazoyer,
R. Annunziata,
F. Boulanger
[show abstract]
[hide abstract]
ABSTRACT: This paper investigates material and electrical properties of a new chalcogenide alloy for Phase-Change Memories (PCM): Carbon-doped GeTe (named GeTeC). First, several physico-chemical, optical and electrical analyses have been performed on full-sheet chalcogenide depositions in order to understand the intrinsic GeTeC phase-change behavior, and to characterize structure and composition of amorphous and crystalline states. Then, GeTeC with two different Carbon doping (4% and 10%) has been integrated in pillar-type analytical PCM cells. Physico-chemical and electrical data indicate that GeTeC is characterized by a much more stable amorphous phase compared to undoped GeTe. Thus, GeTeC offers a slower programming speed versus GeTe, but an improved data retention at high temperature. Finally, we argue that GeTeC alloy is a promising candidate for future developments of PCM technologies for embedded applications.
Memory Workshop (IMW), 2010 IEEE International; 06/2010
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L. Perniola,
V. Sousa,
A. Fantini,
E. Arbaoui,
A. Bastard,
M. Armand,
A. Fargeix,
C. Jahan,
J.-F. Nodin,
A. Persico, [......],
O. Cueto,
G. Reimbold,
L. Poupinet,
T. Billon,
B. De Salvo,
D. Bensahel,
P. Mazoyer,
R. Annunziata,
P. Zuliani,
F. Boulanger
[show abstract]
[hide abstract]
ABSTRACT: In this letter, we present a study on the electrical behavior of phase-change memories (PCMs) based on a GeTe active material. GeTe PCMs show, first, extremely rapid SET operation (yielding a gain of more than one decade in energy per bit with respect to standard GST PCMs), second, robust cycling, up to 1 ?? 10<sup>5</sup>, with 30-ns SET and RESET stress time, and third, a better retention behavior at high temperature with respect to GST PCMs. These results, obtained on single cells, suggest GeTe as a promising alternative material to standard GST to improve PCM performance and reliability.
IEEE Electron Device Letters 06/2010; · 2.85 Impact Factor
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A. Toffoli,
A. Fantini,
G. Betti Beneventi,
L. Perniola,
R. Kies,
V. Vidal,
J.F. Nodin,
V. Sousa,
A. Persico,
J. Cluzel,
C. Jahan,
S. Maitrejean,
G. Reimbold,
B. DeSalvo,
F. Boulanger
[show abstract]
[hide abstract]
ABSTRACT: The Phase Change Memory (PCM), is one of the most promising concepts, as a replacement of Flash memories that should be put in production in next years. However, even if the robustness of such technology is demonstrated for consumer stand-alone applications with typically GST as phase-change chalcogenide material, data retention at high temperature remains an issue, and seemingly even GST based alloys are not able to respect requirements of automotive embedded applications. That is why material research on alternative chalcogenide materials is still lacking, and thorough electrical characterization at analytical cell level is necessary to evaluate the performances of the integrated material. In this work we introduce this concept and the tests to evaluate new technological steps. In particular, we describe the test system optimization and we examine the full automated sequences used for statistic data collection. First step consist in acquiring the SET-toRESET and RESET-to-SET programming characteristics; then data retention tests follow and eventually the cycling experiment close the run. Several characteristics and graphs illustrate this work displaying the key parameters.
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on; 04/2010
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P. Batude,
M. Vinet,
A. Pouydebasque,
C. Le Royer,
B. Previtali,
C. Tabone,
J.-M. Hartmann,
L. Sanchez,
L. Baud,
V. Carron, [......],
F. Allain,
V. Mazzocchi,
D. Lafond,
O. Thomas,
O. Cueto,
N. Bouzaida,
D. Fleury,
A. Amara,
S. Deleonibus,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4¿ of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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P. Batude,
M. Vinet,
A. Pouydebasque,
C. Le Royer,
B. Previtali,
C. Tabone,
L. Clavelier,
S. Michaud,
A. Valentian,
O. Thomas, [......], A. Toffoli,
F. Allain,
P. Grosgeorges,
V. Mazzochi,
L. Tosti,
F. Andrieu,
J.-M. Hartmann,
D. Lafond,
S. Deleonibus,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect control down to L<sub>G</sub> = 50 nm. Both gains in density and performance have been studied with advanced design rules. Processing CMOS on each layer leads to an average 40% density improvement as compared to 2D standard layout.
VLSI Technology, 2009 Symposium on; 07/2009
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M. Bocquet,
G. Molas,
L. Perniola,
X. Garros,
J. Buckley,
M. Gely,
J.P. Colonna,
H. Grampeix,
F. Martin,
V. Vidal, A. Toffoli,
B. De Salvo,
S. Deleonibus,
G. Pananakakis,
G. Ghibaudo
[show abstract]
[hide abstract]
ABSTRACT: In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al<sub>2</sub>O<sub>3</sub> bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed, focusing on their impact on memory performance and reliability. Then, a semi-analytical model is developed, which provides a good understanding of the physical mechanisms at the origin of program/erase characteristics.
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European; 10/2008
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P. Leduc,
L. Di Cioccio,
B. Charlet,
M. Rousseau,
M. Assous,
D. Bouchu,
A. Roule,
M. Zussy,
P. Gueguen,
A. Roman, [......],
M. Heitzmann,
J.-P. Nieto,
L. Vandroux,
P.-H. Haumesser,
R. Quenouillere, A. Toffoli,
P. Sixt,
S. Maitrejean,
L. Clavelier,
N. Sillon
[show abstract]
[hide abstract]
ABSTRACT: This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2 mum to 5 mum large copper TSV chains are presented with a TSV resistance <200 mOmega. Substrate noise due to TSV is also considered by TCAD and SPICE simulations in order to define preliminary design rules.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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[show abstract]
[hide abstract]
ABSTRACT: In the damascene processed tracks, the electrical extraction of the metal thickness is reached through a complex analysis. This is due to processing defects such as dishing and erosion, and linewidths decreasing. This work introduces a new test structure, coupled with the temperature coefficient of resistance (TCR) method in Warkusz, F., et al, (1978). This allows an accurate characterization of metal thickness. At the same time, parameters such as sheet resistance and resistivity become easier to extract for statistical processing analysis.
Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on; 04/2008
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S. Monfray,
M.P. Samson,
D. Dutartre,
T. Ernst,
E. Rouchouze,
D. Renaud,
B. Guillaumot,
D. Chanemougame,
G. Rabille,
S. Borel, [......],
J.M. Hartmann,
L. Vandroux,
D. Bensahel, A. Toffoli,
F. Allain,
A. Margin,
L. Clement,
A. Quiroga,
S. Deleonibus,
T. Skotnicki
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we demonstrate the first successful integration of "localized SOI" devices integrated with HfO<sub>2</sub>/TiN gate stack on dedicated areas of bulk CMOS substrates. We propose a low cost innovative approach based on the SON technology, where the buried sacrificial SiGe layer can be removed directly from the edges of the active area in a self-aligned process, to form an entire fully-depleted structure isolated from the substrate. NMOS devices with gate length down to 32 nm are demonstrated on 6 nm Si-films, allowing the control of I<sub>off</sub> current down to 0.1 nA/mum for 440 muA/mum I<sub>on</sub> @Vdd=1.1 V. We also demonstrated the impact of the TiN (as metal gate) thickness and compressive CESL (contact etch stop layer) boosters for ultra-thin film PMOS, allowing +15% and +22% additional improvement in performances, respectively. This localized-SOI approach is dedicated to low power devices where the leakage reduction is crucial. The possibility for power management is also demonstrated thank to the very thin buried dielectric and to the ground-plane implantations, allowing body factor as high as 80 mV/Von short devices.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
