Yanfeng Wang

Pennsylvania State University, University Park, Maryland, United States

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Publications (11)46.63 Total impact

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    ABSTRACT: Axially doped (n+-p--n+) silicon nanowires were synthesized using the vapor-liquid-solid technique by sequentially modulating the introduction of phosphine to the inlet gas stream during growth from a silane source gas. Top-gate and wrap-around-gate metal oxide semiconductor field-effect transistors that were fabricated after thermal oxidation of the silicon nanowires operate by electron inversion of the p- body segment and have significantly higher on-state current and on-to-off state current ratios than do uniformly p- -doped nanowire field-effect devices. The effective electron mobility of the devices was estimated using a four-point top-gate structure that excludes the source and drain contact resistance and was found to follow the expected universal inversion layer mobility versus effective electric field trend. The field-effect properties of wrap-around-gate devices are less sensitive to global-back-gate bias and thus provide better electrostatic control of the nanowire channel. These results demonstrate the ability to tailor the axial doping profile of silicon nanowires for future planar and vertical nanoelectronic applications.
    Nano Letters 01/2009; 8(12):4359-64. DOI:10.1021/nl8022059 · 13.59 Impact Factor
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    ABSTRACT: The oxidation of unintentionally doped p -type silicon nanowires grown by the vapor-liquid-solid (VLS) method and their integration into top-gated field effect transistors is reported. Dry thermal oxidation of as-grown silicon nanowires with diameters ranging from 20 to 400 nm was carried out at 700 and 900 ° C with or without the addition of a chlorinated gas source. The oxidation rate was strongly dependent on the as-grown nanowire diameter, with the large-diameter nanowires oxidizing up to five times faster than the smallest nanowires at 900 ° C . At each diameter, the addition of trichloroethane (TCA) enhanced the rate compared to oxidation in pure O <sub>2</sub> . Top-gated field effect transistors fabricated from nanowires oxidized at 700 ° C had significantly less hysteresis in their subthreshold properties when TCA was added, but oxidation at 900 ° C with or without TCA provided hysteresis-free devices with improved subthreshold slope. Such enhancements in the electrical properties are expected based on advances in planar silicon process technology and emphasizes the importance of incorporating these techniques for VLS-grown nanowire devices.
    Journal of Vacuum Science & Technology A Vacuum Surfaces and Films 06/2008; 26(3-26):370 - 374. DOI:10.1116/1.2899333 · 2.14 Impact Factor
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    ABSTRACT: Engineering materials at the nanoscale by combining controlled nanomaterial synthesis and directed assembly methods offers the potential to create new electronic and optical devices with improved performance and functionality. Semiconductor nanowires have been of particular interest as a model system for studying new physical phenomena arising from their scaled geometries as well as for applications in high performance vertical transistors, thin film electronic, electro-optical, and sensing devices and circuits. However, the use of relatively immature nanowire growth, in-situ doping, and device integration processes have made it difficult to elucidate and compare the electrical transport properties across different device platforms (e.g., nanowire versus planar) and length scales. This talk will describe recent results showing that thermally-oxidized in-situ axially-doped n+-p--n+ and p+-n--p+ silicon nanowires (20 to 50 run in diameter) grown by the vapor-liquid-solid technique can be used to fabricate stable and reproducible n- and p-channel top-gate and wrap-around-gate field effect transistors (FETs) that operate by inversion ofthe channel and have both high on-state current (Ion) and on/off-state current ratio (Ion/Ioff). Control measurements using back-gated device structures that separately probe the properties of the heavily-doped source/drain regions and lightly-doped channel region confirm that radial thin film deposition on the channel is prevented during vapor-liquid-solid growth of the second heavily-doped nanowire segment, which is necessary for fabricating complementary field effect transistors using these silicon nanowires. The effective mobility estimated from the measured channel resistance of n+-p--n+ and p+-n--p+ silicon nanowire FETs having 1 ?m-long channels will be provided and rel- ated to planar devices. Finally, the properties of the top-gate and wrap-around-gate n- and p-channel silicon nanowire FETs will be compared as a function of global back gate bias.
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    ABSTRACT: The solid-state reaction between platinum and silicon nanowires grown by the vapor-liquid-solid technique was studied. The reaction product PtSi is an attractive candidate for contacts to p-type silicon nanowires due to the low barrier height of PtSi contacts to p-type Si in the planar geometry, and the formation of PtSi was the motivation for our study. Silicidation was carried out by annealing Pt on Si nanowires from 250 to 700 degrees C, and the reaction products were characterized by transmission electron microscopy. Strikingly different morphologies of the reacted nanowires were observed depending on the annealing temperature, platinum film thickness, silicon nanowire diameter, and level of unintentional oxygen contamination in the annealing furnace. Conversion to PtSi was successfully realized by annealing above 400 degrees C in purified N2 gas. A uniform morphology was achieved for nanowires with an appropriate combination of Si nanowire diameter and Pt film thickness to form PtSi without excess Pt or Si. Similar to the planar silicidation process, oxygen affects the nanowire silicidation process greatly.
    Nano Letters 04/2007; 7(3):818-24. DOI:10.1021/nl062393r · 13.59 Impact Factor
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    ABSTRACT: First Page of the Article
    Device Research Conference, 2006 64th; 07/2006
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    ABSTRACT: Phosphine (PH3) was investigated as an n-type dopant source for Au-catalyzed vapor-liquid-solid (VLS) growth of phosphorus-doped silicon nanowires (SiNWs). Transmission electron microscopy characterization revealed that the as-grown SiNWs were predominately single crystal even at high phosphorus concentrations. Four-point resistance and gate-dependent conductance measurements confirmed that electrically active phosphorus was incorporated into the SiNWs during VLS growth. A transition was observed from p-type conduction for nominally undoped SiNWs to n-type conduction upon the introduction of PH3 to the inlet gas. The resistivity of the n-type SiNWs decreased by approximately 3 orders of magnitude as the inlet PH3 to silane (SiH4) gas ratio was increased from 2 x 10(-5) to 2 x 10(-3). These results demonstrate that PH3 can be used to produce n-type SiNWs with properties that are suitable for electronic and optoelectronic device applications.
    Nano Letters 12/2005; 5(11):2139-43. DOI:10.1021/nl051442h · 13.59 Impact Factor
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    ABSTRACT: The Si nanowires (SiNWs) used in these studies were synthesized by vapor-liquid-solid (VLS) growth from Au catalyst particles using 10% SiH <sub>4</sub> in H<sub>2</sub> as the silicon gas source, trimethylboron (TMB) as the p-type dopant, and phosphine (PH<sub>3</sub>) as the n-type dopant. The ratio of TMB or PH<sub>3</sub> to SiH<sub>4</sub> was varied from 0 to 10<sup>-2</sup> to modulate the hole or electron carrier concentration in the SiNWs. Following growth, the Au catalyst particles were removed from the tips of the as-grown SiNWs, and the wires were cleaned using a modified RCA process prior to dry thermal oxidation at 700degC for 4 hours. Transmission electron microscopy studies show that the interface between the SiNW core and the -10 nm thick SiO<sub>2 </sub> shell is smooth and uniform. These SiNWs were integrated onto a top- and back-gated test structure by electrofludically aligning individual wires between pairs of large area electrodes. Source and drain (S/D) contacts were defined by first removing the oxide shell at the NW tips and then lifting off Ti(100nm)/Au(60nm) metal. Non-self-aligned 3 mum long top gates comprised of Ti(60nm)/Au(40nm) were then deposited on the SiO<sub>2</sub> shell, which served as the top gate dielectric. The n<sup>++</sup> Si substrate coated with 100 nm of LPCVD Si<sub>3</sub>N<sub>4</sub> was used as a back gate in these structures
    Device Research Conference Digest, 2005. DRC '05. 63rd; 02/2005
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    ABSTRACT: Trimethylboron (TMB) was investigated as a p-type dopant source for the vapor–liquid–solid growth of boron-doped silicon nanowires (SiNWs). The boron concentration in the nanowires was measured using secondary ion mass spectrometry and results were compared for boron-doping using TMB and diborane (B2H6) sources. Boron concentrations ranging from 1×1018 to 4×1019 cm−3 were obtained by varying the inlet dopant∕SiH4 gas ratio. TEM characterization revealed that the B2H6-doped SiNWs consisted of a crystalline core with a thick amorphous Si coating, while the TMB-doped SiNWs were predominantly single crystal even at high boron concentrations. The difference in structural properties was attributed to the higher thermal stability and reduced reactivity of TMB compared to B2H6. Four-point resistivity and gate-dependent conductance measurements were used to confirm p-type conductivity in the TMB-doped nanowires and to investigate the effect of dopant concentration on nanowire resistivity.
    Applied Physics Letters 10/2004; 85(15):3101-3103. DOI:10.1063/1.1792800 · 3.52 Impact Factor
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    ABSTRACT: There has been considerable interest in bottom-up integration of semiconductor nanowires for their application in future logic, memory, and sensor circuits. The ability to integrate field effect devices with p- and n-type conduction channels is a challenge that must be overcome to fabricate complementary logic circuits using such technologies. In this talk, we present the results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type, and n-type silicon nanowires (SiNWs). These results emphasize that future efforts must address the source of the high p-type background doping concentration in vapor-liquid-solid grown SiNWs to facilitate improvements in the properties of n-channel devices.
    Device Research Conference, 2004. 62nd DRC. Conference Digest [Includes 'Late News Papers' volume]; 07/2004
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    ABSTRACT: The fabrication of semiconductor nanowires, in which composition, size and conductivity can be controlled in both the radial and axial direction of the wire is of interest for fundamental studies of carrier confinement as well as nanoscale device development. In this study, group IV semiconductor nanowires, including Si, Ge and SixGe1-x alloy nanowires were fabricated by vapor-liquid-solid (VLS) growth using gaseous precursors. In the VLS process, gold is used to form a liquid alloy with Si and Ge which, upon supersaturation, precipitates a semiconductor nanowire. Nanoporous alumina membranes were used as templates for the VLS growth process, in order to control the diameter of the nanowires over the range from 45 nm to 200 nm. Intentional p-type and n-type doping was achieved through the addition of either trimethylboron, diborane or phosphine gas during nanowire growth. The electrical properties of undoped and intentionally doped silicon nanowires were characterized using field-assisted assembly to align and position the wires onto pre-patterned test bed structures. The depletion characteristics of back-gated nanowire structures were used to determine conductivity type and qualitatively compare dopant concentration. SiGe and SiGe/Si axial heterostructure nanowires were also prepared through the addition of germane gas during VLS growth. The Ge concentration in the wires was controllable over the range from 12 % to 25% by varying the inlet GeH4/SiH4 ratio.© (2004) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
  • [Show abstract] [Hide abstract]
    ABSTRACT: The fabrication of semiconductor nanowires, in which composition, size and conductivity can be controlled in both the radial and axial direction of the wire is of interest for fundamental studies of carrier confinement as well as nanoscale device development. In this study, group IV semiconductor nanowires, including Si, Ge and SixGe1-x alloy nanowires were fabricated by vapor-liquid-solid (VLS) growth using gaseous precursors. In the VLS process, gold is used to form a liquid alloy with Si and Ge which, upon supersaturation, precipitates a semiconductor nanowire. Nanoporous alumina membranes were used as templates for the VLS growth process, in order to control the diameter of the nanowires over the range from 45 nm to 200 nm. Intentional p-type and n-type doping was achieved through the addition of either trimethylboron, diborane or phosphine gas during nanowire growth. The electrical properties of undoped and intentionally doped silicon nanowires were characterized using field-assisted assembly to align and position the wires onto pre-patterned test bed structures. The depletion characteristics of back-gated nanowire structures were used to determine conductivity type and qualitatively compare dopant concentration. SiGe and SiGe/Si axial heterostructure nanowires were also prepared through the addition of germane gas during VLS growth. The Ge concentration in the wires was controllable over the range from 12 % to 25% by varying the inlet GeH4/SiH4 ratio.
    Proceedings of SPIE - The International Society for Optical Engineering 06/2004; DOI:10.1117/12.533572 · 0.20 Impact Factor

Publication Stats

285 Citations
46.63 Total Impact Points

Institutions

  • 2004–2009
    • Pennsylvania State University
      • • Department of Electrical Engineering
      • • Department of Materials Science and Engineering
      University Park, Maryland, United States
    • William Penn University
      Worcester, Massachusetts, United States