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ABSTRACT: The benefit of La-Al-O higher-k gate dielectrics is maximized by optimizing the Al/(La+Al) atomic ratio. The Al/(La+Al) atomic ratio modulates the band gap, dielectric constant, and interface dipoles, resulting in change of energy band alignment. The La-Al-O film with an Al/(La+Al) atomic ratio of 0.25 yields a maximum leakage current reduction exceeding HfO<sub>2</sub> and La<sub>2</sub>O<sub>3</sub>, owing to the optimized band alignment structure. Moreover, a SiON underlayer instead of SiO<sub>2</sub> enables additional equivalent oxide thickness scaling down to 7.4 Å while maintaining the fully reduced leakage current with a gate-first process.
IEEE Electron Device Letters 04/2011; · 2.85 Impact Factor
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T. Ando,
M.M. Frank,
K. Choi,
C. Choi,
J. Bruley,
M. Hopstaken,
M. Copel,
E. Cartier,
A. Kerber, A. Callegari,
D. Lacey,
S. Brown,
Q. Yang,
V. Narayanan
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ABSTRACT: We demonstrate a novel ¿remote interfacial layer (IL) scavenging¿ technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO<sub>2</sub>-based MOSFET high-¿ gate dielectric. Intrinsic effects of IL scaling on carrier mobility are clarified using this method. We reveal that the mobility degradation observed for La-containing high-¿ is not due to the La dipole but due to the intrinsic IL scaling effect, whereas an Al dipole brings about additional mobility degradation. This unique nature of the La dipole enables aggressive EOT scaling in conjunction with IL scaling for the 16 nm technology node without extrinsic mobility degradation.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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K. Choi,
H. Jagannathan,
C. Choi,
L. Edge,
T. Ando,
M. Frank,
P. Jamison,
M. Wang,
E. Cartier,
S. Zafar,
J. Bruley,
A. Kerber,
B. Linder, A. Callegari,
Q. Yang,
S. Brown,
J. Stathis,
J. Iacoponi,
V. Paruchuri,
V. Narayanan
[show abstract]
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ABSTRACT: We report for the first time that extreme EOT scaling and low n/p VTHs can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low V<sub>TH</sub>s and competitive carrier mobilities in this work demonstrate the gate stack technology that is consistent with the sub-22 nm node requirements.
VLSI Technology, 2009 Symposium on; 07/2009
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ABSTRACT: We report the following results for metal/HfO<sub>2</sub>/oxide stacks, (i) The energy level band diagram of HfO<sub>2</sub>/SiO<sub>2</sub> stacks is experimentally determined for the first time; the conduction band offset between HfO<sub>2</sub> and interfacial SiO<sub>2</sub> is estimated to be 2.05 eV. (ii) Work functions of W, Re and TaSiN are measured for HfO<sub>2</sub>/SiO<sub>2</sub>/Si and SiO<sub>2</sub>/Si stacks: work functions exhibit no Fermi pinning effect in HfO<sub>2</sub>, unlike previous report by Schaeffer et al in 2004. (iii) The impact of metal gate deposition on its work function and the oxide charge density is investigated. Measurements show that the tungsten work function is independent of deposition time and method (CVD vs. sputtering). However, oxide charge density (Q<sub>0X</sub>) depends both on the deposition time and method: Q<sub>0X</sub> is positively charged for CVD and negatively charged for sputtered depositions. Also, Q<sub>0X</sub> increases with W deposition time.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: Negative bias temperature instability (NBTI) causes the threshold voltage (V,) to shift with stressing time and is an increasingly important reliability issue with CMOS scaling. To continue scaling, FinFETs and FETs on hybrid orientation substrates are two new technologies that are under consideration. Recently, higher NBTI was reported for FinFETs in comparison to planar FETs and this higher NBTI was attributed to <110> orientation of the fin sidewall. In this paper, we present a systematic study of NBTI in <110> and <100> orientation pFETs with thermal SiON, plasma nitrided SiON, and thermal SiON/HfO<sub>2</sub> as gate dielectrics. The objective of the study is to compare NBTI in pFETs as a function of substrate orientation and gate dielectric films and to apply a recently proposed physics based model to the NBTI data for gaining insights into NBTI. Three main results are reported. (I) Measurements show that the NBTI is larger for <110> orientation in comparison to <100> for the thermal SiON and SiON/HfO<sub>2</sub> pFETs. In contrast, NBTI is independent of substrate orientation for the plasma nitrided SiON pFETs. (II) NBTI induced increase in positive charge density is larger for the plasma nitrided SiON pFETs in comparison to those for thermal SiON and SiON/HfO<sub>2</sub> pFETs. (III) The model provides good fits to V, shift versus stressing time data for various pFETs. Using the model fits, V<sub>t</sub> shifts after 10 years stressing are estimated and compared for various pFETs. Model parameters attribute the enhanced NBTI in <110> orientation pFETS to higher bonded hydrogen densities at the oxide/Si interface for the case of thermal SiON and SiON/HfO<sub>2</sub> pFETs. Since model fitting parameters are independent of substrate orientation for pFETS with plasma nitrided SiON. a possible explanation is that the incorporation of bonded hydrogen at the silicon interface is determined predominantly by the plasma nitridation conditions.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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E.P. Gusev,
V. Narayanan,
S. Zafar,
C. Cabral Jr,
E. Carrier,
N. Bojarczuk, A. Callegari,
R. Carruthers,
M. Chudzik,
C. D'Emic,
E. Duch,
P. Jamison,
P. Kozlowski,
D. LaTulipe,
K. Maitra,
F.R. McFeely,
J. Newbury,
V. Paruchuri,
M. Steen
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ABSTRACT: A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or T<sub>inv</sub>, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates); (ii) high-k dielectric material (HfO<sub>2</sub>, HfO<sub>2</sub>:N, HfSiO, HfSiON, ZrO<sub>2</sub>, Al<sub>2</sub>O<sub>3</sub>); (iii) high-k deposition technique (MOCVD vs. ALD); (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-k layer and poly-Si plays a major role in charge trapping degradation.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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A. Callegari,
P. Jamison,
E. Carrier,
S. Zafar,
E. Gusev,
V. Narayanan,
C. D'Emic,
D. Lacey,
F.M. Feely,
R. Jammy,
M. Gribelyuk,
J. Shepard,
W. Andreoni,
A. Curioni,
C. Pignedoli
[show abstract]
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ABSTRACT: Electron mobilities of W/HfO<sub>2</sub> stacks were found to increase monotonically with annealing temperature with little (peak) or no degradation (1 MV/cm) when compared to poly-Si devices using conventional oxides. For stacks annealed at high temperature charge pumping curves indicate low interface states densities of ∼5 × 10<sup>10</sup> charges/cm<sup>2</sup>. Mobility enhancement can also be attributed to a structural change in the HfO<sub>2</sub> gate stack rather than due to only interfacial layer re-growth.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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E.P. Gusev,
C. Cabral Jr,
B.P. Under,
Y.H. Kim,
K. Maitra,
E. Carrier,
H. Nayfeh,
R. Amos,
G. Biery,
N. Bojarczuk, [......],
H. Ng,
P. Nguyen,
J. Newbury,
V. Paruchuri,
R. Rengarajan,
G. Shahidi,
A. Steegen,
M. Steen,
S. Zafar,
Y. Zhang
[show abstract]
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ABSTRACT: The key result in this work is that FUSI/HfSi<sub>x</sub>O<sub>y</sub> gate stacks offer both significant gate leakage reduction (due to high-κ) and drive current improvement at T<sub>inv</sub> ∼ 2 nm (due to: (i) elimination of poly depletion effect, ∼ 0.5 nm, and (ii) the high mobility of HfSi<sub>x</sub>O<sub>y</sub>). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)∼ -0.4 V and Vt(NFET) ∼ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V<sub>t</sub> stability) was found in the case of NiSi/ HfSi<sub>x</sub>O<sub>y</sub> compared to the same gate electrode with HfO<sub>2</sub> dielectric.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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[show abstract]
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ABSTRACT: A model for the negative bias temperature instability (NBTI) is proposed. Unlike previous empirical models, this model is derived from physics principles. The model attributes NBTI to de-passivation of SiO<sub>2</sub>/Si interface and its two distinguishing features are: application of statistical mechanics to calculate depassivated site density increase and the assumption that the hydrogen diffusion is dispersive. The model is verified using new and published NBTI data for SiO<sub>2</sub>/poly, SiON/W and HfO<sub>2</sub>/W pFETs. A comparison between high κ and conventional oxide is made.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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E. Cartier,
V. Narayanan,
E.P. Gusev,
P. Jamison,
B. Linder,
M. Steen,
K.K. Chan,
M. Frank,
N. Bojarczuk,
M. Copel, [......], A. Callegari,
M. Gribelyuk,
M.P. Chudzik,
C. Cabral Jr,
R. Carruthers,
C. D'Emic,
J. Newbury,
D. Lacey,
S. Guha,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: The flatband/threshold voltages (V<sub>fb</sub>/V<sub>t</sub>) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO<sub>2</sub> at poly-Si deposition temperatures is identified as the root cause for the poor V<sub>fb</sub>/V<sub>t</sub> control. No improvement in V<sub>t</sub> control is obtained by engineering physically closed Si<sub>3</sub>N<sub>4</sub> barrier layers on HfO<sub>2</sub>. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V<sub>fb</sub>/V<sub>t</sub> shifts are observed with HfO<sub>2</sub>. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al<sub>2</sub>O<sub>3</sub> cap layers on silicates.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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V. Narayanan, A. Callegari,
F.R. McFeely,
K. Nakamura,
P. Jamison,
S. Zafar,
E. Cartier,
A. Steegen,
V. Ku,
P. Nguyen, [......],
Y. Kawano,
D. Lacey,
Y. Li,
E. Sikorski,
F. Duch,
H. Ng,
C. Wann,
R. Jammy,
M. Ieong,
G. Shahidi
[show abstract]
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ABSTRACT: Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO<sub>2</sub>. T<sub>inv</sub> as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better have been achieved. For the first time we report low damage CVD processes for achieving dual workfunction metal gates in contrast to most reports in literature. Excellent hole mobility has been obtained for aggressive stacks. It is further observed that electron mobility optimization is critically dependent on specific electrode and interface layer combinations along with post deposition processing even for nominally identical HfO<sub>2</sub> layers.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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[show abstract]
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ABSTRACT: The thermal stability of polycrystalline silicon (poly-Si)/ZrO2 interface was significantly enhanced when the poly-Si was plasma deposited using silane heavily diluted in He. With regard to this process, transmission electron microscopy shows a sharp poly-Si/ZrO2 interface that is stable at 1000 °C. When the poly-Si was deposited by chemical vapor deposition using undiluted silane gas, transmission electron microscopy shows strong reactions at the poly-Si/ZrO2 interface when annealed at 1000 °C. The increased stability can be attributed to He dilution, which may prevent hydrogen from reducing the metal oxide. Another explanation may be directly related to He-excited plasma, which is known to produce denser and more stable films. © 2002 American Institute of Physics.
Applied Physics Letters 11/2002; 81(22):4157-4158. · 3.84 Impact Factor
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ABSTRACT: Interface reactions in Si/SiOx(Ny)/ZrO2 and Si/SiOx(Ny)/ZrO2/poly-Si gate stacks have been studied by high-resolution transmission electron microscopy. In the case of an uncapped stack ZrSi and ZrSi2 phases form during an ultrahigh vacuum anneal at temperatures above 900 °C. Both phases show an island-type growth with an epitaxial relationship with Si (100). Gate dielectric stacks with a poly-Si cap are found to be thermally unstable at T=1000 °C, so that the reaction is initiated at the ZrO2/poly-Siinterface. Here a different reaction mechanism is identified, which involves the reduction of ZrO2 and the growth of a bottom interfacial layer between ZrOx and Si. Replacement of the bottom SiO2 layer by an ultrathin Si oxinitride does not completely suppress these interfacial reactions at T⩾1000 °C. We suggest that control of the poly-Si/ZrO2 interfacial reactions may be an important factor in modifying the thermal stability of a stack. These results shed a new light on understanding the material challenges involved in the integration of ZrO2 for the next generation of complementary metal–oxide–semiconductor technologies. © 2002 American Institute of Physics.
Journal of Applied Physics 07/2002; 92(3):1232-1237. · 2.17 Impact Factor
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[show abstract]
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ABSTRACT: A method for measuring metal barrier heights, work function and fixed charge densities in metal / SiO <sub>2</sub>/ Si capacitors is developed and verified. This technique is based on theoretical studies of tunneling phenomenon through a potential barrier and requires measurement of current versus voltage sweeps at two different temperatures. Unlike the commonly used capacitance method, this method does not require a set of capacitors with different gate oxide thickness for determining work functions and fixed charge densities in metal / SiO <sub>2</sub>/ Si capacitors. Hence, this method provides a fast means for investigating metal work function and fixed charge densities in metal-gated SiO <sub>2</sub> capacitors. © 2002 American Institute of Physics.
Applied Physics Letters 07/2002; · 3.84 Impact Factor
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[show abstract]
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ABSTRACT: Charge trapping in Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub> nFETs is studied. The dependence of threshold voltage, subthreshold slope and gate leakage currents are investigated as a function of stressing time, voltage and temperature. Based on the experimental data, a model is developed for predicting threshold voltage shifts as a function stressing time. The model is compatible with both Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub> data. Using the model, threshold voltage shifts after 10 years of stressing is predicted and trapping capture cross sections are estimated. A comparison between Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub> is also made.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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[show abstract]
[hide abstract]
ABSTRACT: Hafnium oxides and hafnium silicate films were investigated as a possible replacement for the SiO2 gate dielectric. Hafnium oxide films were formed by reactive sputtering from a single Hf oxide target in a predominantly Ar atmosphere containing small additions of oxygen. Hafnium silicates were made by adding a He-diluted silane gas for Si incorporation. By changing the silane gas flow, different Si atomic concentrations were incorporated into the Hf oxide films. Depositions were performed with the substrate held at temperatures of 22 °C and 500 °C. The chemical composition of the films was determined with nuclear techniques. Optical reflectivity was used to measure the optical band gap. The film morphology was investigated by transmission electron microscopy (TEM) and the electrical properties were measured with capacitance–voltage and current–voltage measurements using aluminum gate capacitors. TEM and electrical measurement showed that a SiO2 interfacial layer of about 3 nm formed at the Si interface due to the oxidizing sputter ambient. This precluded the growth of Hf based high-K films with small equivalent thickness. After correction for the interfacial oxide layer, the dielectric constant was found to decrease from about 21 for Hf oxide to about 4–5 for the Hafnium silicates with low Hf content (3 at. % Hf and 32 at. % Si). The optical band gap was found to increase from 5.8 eV for Hf oxide to about 7 eV for the silicate films. After annealing at 1000 °C followed by a 300 °C postmetallization anneal, negligible flat band voltage shift were measured on hafnium silicate films and good interface passivation was observed. However, leakage currents increased due to the high temperature processing. © 2001 American Institute of Physics.
Journal of Applied Physics. 12/2001; 90(12):6466-6475.
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P Chaudhari,
J Lacey,
J Doyle,
E Galligan,
S C Lien, A Callegari,
G Hougham,
N D Lang,
P S Andry,
R John, [......],
J Stöhr,
Y Nakagawa,
Y Katoh,
Y Saitoh,
K Sakai,
H Satoh,
S Odahara,
H Nakano,
J Nakagaki,
Y Shiota
[show abstract]
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ABSTRACT: The technique used to align liquid crystals-rubbing the surface of a substrate on which a liquid crystal is subsequently deposited-has been perfected by the multibillion-dollar liquid-crystal display industry. However, it is widely recognized that a non-contact alignment technique would be highly desirable for future generations of large, high-resolution liquid-crystal displays. A number of alternative alignment techniques have been reported, but none of these have so far been implemented in large-scale manufacturing. Here, we report a non-contact alignment process, which uses low-energy ion beams impinging at a glancing angle on amorphous inorganic films, such as diamond-like carbon. Using this approach, we have produced both laptop and desktop displays in pilot-line manufacturing, and found that displays of higher quality and reliability could be made at a lower cost than the rubbing technique. The mechanism of alignment is explained by adopting a random network model of atomic arrangement in the inorganic films. Order is induced by exposure to an ion beam because unfavourably oriented rings of atoms are selectively destroyed. The planes of the remaining rings are predominantly parallel to the direction of the ion beam.
Nature 06/2001; 411(6833):56-9. · 36.28 Impact Factor
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E.P. Gusev,
D.A. Buchanan,
E. Cartier,
A. Kumar,
D. DiMaria,
S. Guha, A. Callegari,
S. Zafar,
P.C. Jamison,
D.A. Neumayer, [......],
C. D'Emic,
P. Kozlowski,
K. Chan,
N. Bojarczuk,
L.-A. Ragnarsson,
P. Ronsheim,
K. Rim,
R.J. Fleming,
A. Mocuta,
A. Ajmera
[show abstract]
[hide abstract]
ABSTRACT: Reviews recent progress in and outlines the issues for high-K
high-temperature (~1000°C) poly-Si CMOS processes and devices and
also demonstrate possible solutions. Specifically, we discuss device
characteristics such as gate leakage currents, flatband voltage shifts,
charge trapping, channel mobility, as well as integration and processing
aspects. Results on a variety of high-K candidates including HfO<sub>2
</sub>, Al<sub>2</sub>O<sub>3</sub>,
HfO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>, ZrO<sub>2</sub>, silicates,
and AlN<sub>y</sub>(O<sub>x</sub>) deposited on silicon by different
deposition techniques are shown to illustrate the complex issues for
high-K dielectric integration into current Si technology
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
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D.A. Buchanan,
E.P. Gusev,
E. Cartier,
H. Okorn-Schmidt,
K. Rim,
M.A. Gribelyuk,
A. Mocuta,
A. Ajmera,
M. Copel,
S. Guha,
N. Bojarczuk, A. Callegari,
C. D'Emic,
P. Kozlowski,
K. Chan,
R.J. Fleming,
P.C. JAmison,
I. Brown,
R. Arndt
[show abstract]
[hide abstract]
ABSTRACT: This work demonstrates the integration of Al<sub>2</sub>O<sub>3
</sub> gate-dielectrics into a sub 0.1 μm n-MOS process using
polycrystalline silicon gates, Devices incorporating
Al<sub>2</sub>O<sub>3</sub> films with a dielectric constant ε-11
and electrical thickness t<sub>qm</sub><1.5 nm have been fabricated.
Gate leakage currents are ~100 times lower than those found in SiO<sub>2
</sub> films of equivalent thickness. Encouraging device characteristics
are shown. Charging due to slow states and/or fixed charge have been
shown to be in the 100 mV range which may be related to the somewhat
reduced mobility. The room temperature reliability of these devices
based upon the values of β (Weibull slope) and γ (voltage
acceleration) suggest that the Al<sub>2</sub>O<sub>3</sub> lifetime may
exceed that of SiO<sub>2</sub> films
Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
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[show abstract]
[hide abstract]
ABSTRACT: Thin film transistors (TFT) comprising pentacene as the
semiconductor layer and an amorphous metal oxide gate insulators with a
dielectric constant around 16 were fabricated and tested. Field effect
mobility values up to 0.6 cm<sup>2</sup> V<sup>-1</sup> s<sup>-1</sup>
with subthreshold slopes up to 0.3 V/decade and current modulation
higher than 10<sup>5</sup> were obtained at operating voltages ranging
from 4 to 15 V. TFTs fabricated at room temperature on transparent
plastic substrates and exhibiting similar transport characteristics were
demonstrated
Device Research Conference Digest, 1999 57th Annual; 02/1999
