[Show abstract][Hide abstract] ABSTRACT: This thesis describes the utilization of silicon nanowires and molecular films towards the realization of nanoscale electronics. The key enabling technology is the method in which the silicon nanowires are produced—the superlattice nanowire pattern transfer (SNAP) method. The SNAP method allows for the simultaneous formation and alignment of metal or semiconducting nanowires using a template-mediated approach. High-performance n- and p-type silicon nanowire field-effect transistors (FETs) were demonstrated. These FETs exhibited consistent performance and strong performance metrics such as high on/off ratios, high on-currents, high mobilities and low subthreshold swings. Due to the nanowire’s large surface-area-to-volume ratio, surface states were shown to dominate performance, especially for the n-type FETs. Reducing the number of surface states improved performance significantly. N- and p-type silicon nanowire FETs were integrated into complementary symmetry (CS) logic circuits. This required the development of a pattern doping technique that allowed for spatial control of doped regions. The inverter circuit was fabricated and tested. A gain of ~ 5 was consistently measured from 7 working inverter circuits. This demonstration provided the foundation for the eventual fabrication and characterization of the other Boolean logic functions. A methodology was developed that optimizes the design of high-performance logic circuits constructed from Si NW p- and n-type FETs. Circuit performance can be predicted from individual fabricated NW FETs before prototype circuits are manufactured, resulting in a faster and more efficient design process. These results suggest design options for fabricating high performance NW circuits, which can then be implemented experimentally. The effectiveness of this methodology is shown by optimizing the gain of Si NW complementary symmetry inverter from an initially measured value of 8 to a gain of 45. Lastly, methods to covalently attach electronically interesting molecules via microcontact printing onto gold and silicon substrates were developed. In these studies, the Cu(I)-catalyzed azide-alkyne cycloaddition (CuAAC) reaction was used to form the covalent attachment. It was observed that the reaction would proceed readily by replacing the Cu catalyst in the stamp ink by a Cu coating on the stamp directly. This reaction proceeded quickly on both azide-terminated monolayers on Au and Si(111) substrates.
[Show abstract][Hide abstract] ABSTRACT: Minting a Stamp: The preparation of copper metal-coated elastomeric stamps and their use in catalyzing the Cu-catalyzed azide-alkyne cycloaddition reaction heterogeneously through microcontact printing is described. This StampCat process is compared to other conventional surface-functionalization techniques, including traditional microcontact printing and solution-surface-based reactions.
Angewandte Chemie International Edition 12/2008; 47(51):9927-32. · 11.34 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.
[Show abstract][Hide abstract] ABSTRACT: This article reviews our recent progress on ultra-high density nanowires (NWs) array-based electronics. The superlattice nanowire
pattern transfer (SNAP) method is utilized to produce aligned, ultra-high density Si NW arrays. We fi rst cover processing
and materials issues related to achieving bulk-like conductivity characteristics from 10 20 nm wide Si NWs. We then discuss
Si NW-based fi eld-effect transistors (FETs). These NWs & NW FETs provide terrifi c building blocks for various electronic
circuits with applications to memory, energy conversion, fundamental physics, logic, and others. We focus our discussion on
complementary symmetry NW logic circuitry, since that provides the most demanding metrics for guiding nanofabrication. Issues
such as controlling the density and spatial distribution of both p-and n-type dopants within NW arrays are discussed, as are
general methods for achieving Ohmic contacts to both p-and n-type NWs. These various materials and nanofabrication advances
are brought together to demonstrate energy effi cient, complementary symmetry NW logic circuits.
Nano Research 06/2008; 1(1):9-21. · 7.39 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The primary metric for gauging progress in the various semiconductor integrated circuit technologies is the spacing, or pitch, between the most closely spaced wires within a dynamic random access memory (DRAM) circuit. Modern DRAM circuits have 140 nm pitch wires and a memory cell size of 0.0408 mum(2). Improving integrated circuit technology will require that these dimensions decrease over time. However, at present a large fraction of the patterning and materials requirements that we expect to need for the construction of new integrated circuit technologies in 2013 have 'no known solution'. Promising ingredients for advances in integrated circuit technology are nanowires, molecular electronics and defect-tolerant architectures, as demonstrated by reports of single devices and small circuits. Methods of extending these approaches to large-scale, high-density circuitry are largely undeveloped. Here we describe a 160,000-bit molecular electronic memory circuit, fabricated at a density of 10(11) bits cm(-2) (pitch 33 nm; memory cell size 0.0011 microm2), that is, roughly analogous to the dimensions of a DRAM circuit projected to be available by 2020. A monolayer of bistable, rotaxane molecules served as the data storage elements. Although the circuit has large numbers of defects, those defects could be readily identified through electronic testing and isolated using software coding. The working bits were then configured to form a fully functional random access memory circuit for storing and retrieving information.
[Show abstract][Hide abstract] ABSTRACT: Statistical numbers of field-effect transistors (FETs) were fabricated from a circuit of 17-nm-wide, 34-nm-pitch Si nanowires boron doped at a level of 10(18) cm-3. Top-gated 4-microm-wide Si nanowire p-FETs yielded low off-currents (approximately 10(-12) A), high on/off ratios (10(5)-10(6)), good on current values (30 microA/microm), high mobilities (approximately 100 cm2/V-s), and low subthreshold swing values (approximately 80 mV/decade between 10(-12) and 10(-10) A increasing to 200 mV/decade between 10(-10)-10(-8) A).
[Show abstract][Hide abstract] ABSTRACT: High density metal cross bars at 17 nm half-pitch were fabricated by nanoimprint lithography. Utilizing the superlattice nanowire pattern transfer technique, a 300-layer GaAs/AlGaAs superlattice was employed to produce an array of 150 Si nanowires (15 nm wide at 34 nm pitch) as an imprinting mold. A successful reproduction of the Si nanowire pattern was demonstrated. Furthermore, a cross-bar platinum nanowire array with a cell density of approximately 100 Gbit/cm(2) was fabricated by two consecutive imprinting processes.
[Show abstract][Hide abstract] ABSTRACT: Since its inception by Avirim and Ratner in 1974, molecular-based electronics has emerged as a promising alternative to scaled CMOS technology and its eventual integration limit. Here we present progress towards an electronically configurable, molecule-based 160,000 Bit random access memory at a Bit density approaching 10^11 Bits/cm^2. This device is based on a cross-bar architecture in which the active switching elements are bi-stable -rotaxane supramolecules sandwiched between perpendicular arrays of SNAP-fabricated  metallic and n-Si nanowires at 34 nm pitch. Challenges in memory fabrication and testing will be discussed.  Science 300, 112 (2003); J. App. Phys. 96, 5921 (2004).
[Show abstract][Hide abstract] ABSTRACT: We describe our research into building integrated molecular electronics circuitry for a diverse set of functions, and with a focus on the fundamental scientific issues that surround this project. In particular, we discuss experiments aimed at understanding the function of bistable rotaxane molecular electronic switches by correlating the switching kinetics and ground state thermodynamic properties of those switches in various environments, ranging from the solution phase to a Langmuir monolayer of the switching molecules sandwiched between two electrodes. We discuss various devices, low bit-density memory circuits, and ultra-high density memory circuits that utilize the electrochemical switching characteristics of these molecules in conjunction with novel patterning methods. We also discuss interconnect schemes that are capable of bridging the micrometre to submicrometre length scales of conventional patterning approaches to the near-molecular length scales of the ultra-dense memory circuits. Finally, we discuss some of the challenges associated with fabricated ultra-dense molecular electronic integrated circuits.
[Show abstract][Hide abstract] ABSTRACT: The development of the superlattice nanowire pattern transfer (SNAP) technique has allowed for the fabrication of highly ordered arrays of hundreds of nanowires (both metallic and semiconducting) at pitches down to 16 nm and aspect ratios up to 10^6. Applications of these nanowire arrays range from bridging length scales via binary-tree demultiplexing , to the development of ultra-dense arrays of molecular switch tunnel junctions (˜ 1 TBit/in^2), to the integration of complementary logic arrays within a crossbar architecture. In addition, at the narrowest pitches the periodicity of the SNAP array is only a few tens of atoms, allowing access to length scales compatible with coherent electronic transport and opening the door to fundamental studies. These topics will be discussed within the context of the flexibility of the SNAP fabrication technique and its wide applicability to a number of both basic and applied challenges in nanoscience/nanotechnology.  Science, 310, 465 (2005).