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ESSDERC, 42nd European Solid-State Device Research Conference, Bordeaux, France; 09/2012
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IEEE Transactions on Electron Devices 09/2012; · 2.32 Impact Factor
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ABSTRACT: A novel 3-D NAND flash memory device, VSAT (Vertical-Stacked-Array-Transistor), has successfully been achieved. The VSAT was realized through a cost-effective and straightforward process called PIPE (planarized-Integration-on-the-same-plane). The VSAT combined with PIPE forms a unique 3-D vertical integration method that may be exploited for ultra-high-density Flash memory chip and solid-state-drive (SSD) applications. The off-current level in the polysilicon-channel transistor dramatically decreases by five orders of magnitude by using an ultra-thin body of 20 nm thick and a double-gate-in-series structure. In addition, hydrogen annealing improves the subthreshold swing and the mobility of the polysilicon-channel transistor.
VLSI Technology, 2009 Symposium on; 07/2009
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K. Galatsis,
A. Khitun,
R. Ostroumov, K.L. Wang,
W.R. Dichtel,
E. Plummer,
J.F. Stoddart,
J.I. Zink,
Jae Young Lee,
Ya-Hong Xie,
Ki Wook Kim
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ABSTRACT: We provide an outlook of some important state variables for emerging nanoelectronic devices. State variables are physical representations of information used to perform information processing via memory and logic functionality. Advances in material science, emerging nanodevices, nanostructures, and architectures have provided hope that alternative state variables based on new mechanisms, nanomaterials, and nanodevices may indeed be plausible. We review and analyze the computational advantages that alternate state variables may possibly attain with respect to maximizing computational performance via minimum energy dissipation, maximum operating switching speed, and maximum device density.
IEEE Transactions on Nanotechnology 02/2009; · 2.29 Impact Factor
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ABSTRACT: We describe a magnetic nanofabric, which may provide a route to building reconfigurable spin-based logic circuits compatible with conventional electron-based devices. A distinctive feature of magnetic nanofabric is that a bit of information is encoded into the phase of the spin wave signal. This makes it possible to transmit information without the use of electric current and to utilize wave interference for useful logic functionality. The basic elements include voltage-to-spin-wave and wave-to-voltage converters, spin waveguides, a spin wave modulator, and a magnetoelectric cell. We illustrate the performance of the basic elements by experimental data and the results of numerical modeling. The combination of the basic elements leads us to construct magnetic circuits for NOT and majority logic gates. Logic gates such as AND, OR, NAND, and NOR are shown as the combination of NOT and reconfigurable majority gates. Examples of computational architectures such as a multibit processor and a cellular nonlinear network are described. The main advantage of the proposed magnetic nanofabric is its ability to realize logic gates with fewer devices than in CMOS-based circuits. Potentially, the area of the elementary reconfigurable majority gate can be scaled down to 0.1 mum<sup>2</sup>. We also discuss the disadvantages and limitations of the magnetic nanofabric.
IEEE Transactions on Magnetics 10/2008; · 1.36 Impact Factor
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ABSTRACT: A 3-D flash memory cell of VRAT (vertical-recess-array-transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (planarized integration on the same plane), which allows for the successful implementation of ultra high density flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.
VLSI Technology, 2008 Symposium on; 07/2008
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ABSTRACT: We consider power dissipation during simple switching in information processing. By considering general two-level system we show that the energy dissipation during errorless switching has a minimum of kTln2 and increases linearly with a switching speed. Also, we find optimal switching function, which minimizes heat dissipation for the given error rate. We present some estimates and compare them with results for the CMOS technology.
Information Technology: New Generations, 2008. ITNG 2008. Fifth International Conference on; 05/2008
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ABSTRACT: Based on projections of the International Roadmap for Semiconductors (ITRS), the continued scaling of complementary metal-oxide semiconductor (CMOS) devices will face severe technical challenges. Among the most critical are power dissipation and device-level variabilities that will make circuit design very difficult. Potential device-level solutions that take advantage of new functional materials, self-assembly processes, low dissipation nanoscale devices, and architectures that aim in sustaining Moore's law beyond the ITRS are discussed in this paper. Two potential paths forward are clear at this point. One path is to continue increasing chip-scale functional throughput by looking at new functional materials at atomic and molecular levels for assembly into new low-power devices with different logic state variables that can better tolerate variabilities. Another distinct approach is to increase chip-scale functionality by exploiting the heterogeneous integration of materials, such as compound semiconductors on silicon as enabled by the unique features in nanoscale epitaxy and self-assembly on a common substrate. This paper will discuss some possible methods forward in maintaining scaled CMOS and going beyond the roadmap.
Proceedings of the IEEE 03/2008; · 6.81 Impact Factor
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ABSTRACT: We compare the transport parameters such as signal attenuation and signal velocity for a spin-wave bus and a conventional electronic transmission line. The spin-wave bus is inferior to the traditional metal interconnects in all figures-of-merit. The realization of integrated spin-wave-based logic circuits will require spin amplifiers to provide gain.
IEEE Transactions on Electron Devices 01/2008; · 2.32 Impact Factor
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ABSTRACT: This paper highlights some new and old techniques that will have important metrology inroads for nanoelectronics beyond CMOS. Traditional electron microscopy techniques are envisioned to remain and play a core role at the nanoscale level, and others such as probing techniques and special holographic imaging will further be enhanced and provide more diverse capabilities. The paper presents metrology techniques for beyond CMOS as presented at the First Metrology for Beyond CMOS workshop hosted by the Focus Center Research Program Center of Functional Engineered Nano Architectonics, the National Science Foundation Nanoscale Science and Engineering Center for Nanoprobing, and the California Institute of Technology (CNSI).
IEEE Transactions on Semiconductor Manufacturing 12/2007; · 0.72 Impact Factor
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ABSTRACT: In recent years, quantum dots have been successfully grown by self-assembling processes. For optoelectronic device applications, the quantum-dot structures have advantages such as reduced phonon scattering, longer carrier lifetime, and lower detector noise due to low-dimensional confinement effect. Comparing to traditional optoelectronic III-V and other materials, self-assembled Ge quantum dots grown on Si substrates have a potential to be monolithically integrated with advanced Si-based technology. In this paper, we describe the growth of self-assembled, guided Ge quantum dots, and Ge quantum-dot superlattices on Si. For dot growth, issues such as growth conditions and their effects on the dot morphology are reviewed. Then vertical correlation and dot morphology evolution are addressed in relation to the critical thickness of Ge quantum-dot superlattices. In addition, we also discuss the quantum-dot p-i-p photodetectors (QDIPs) and n-i-n photodetectors for mid-infrared applications, and the quantum-dot p-i-n photodetectors for 1.3-1.55 mum for communications applications. The wavelength of SiGe p-i-p QDIP can be tuned by the size as grown by various patterning methods. Photoresponse is demonstrated for an n-i-n structure in both the mid-infrared and far-infrared wavelength ranges. The p-i-n diodes exhibit low dark current and high quantum efficiency. The characteristics of fabricated light-emitting diode (LED) devices are also discussed, and room-temperature electroluminescence is observed for Ge quantum-dot LED. The results indicate that Ge dot materials are potentially applicable for mid-infrared (8-12 mum) detectors as well as fiber-optic (1.3-1.55 mum) communications.
Proceedings of the IEEE 10/2007; · 6.81 Impact Factor
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ABSTRACT: Rapid dielectrophoretic (DEP) liquid actuation and dispensing of uniform aqueous droplets on a substrate are implemented for the first time in a silicon-based architecture. Using 1 0 0 Si wafers takes advantage of the high thermal conductivity and extensive semiconductor microfabrication capabilities of silicon. The structures employ a coplanar, three-electrode design to guarantee reproducible dispensing of multiple sessile droplets as small as ∼75 pl. A reduced-order dynamic model provides a predictive relation for the transient liquid motion, which is implemented in an open-loop dynamic control scheme to achieve repeatable production of anywhere from 1 to 23 droplets per structure by controlling voltage on-time.
J. Micromech. Microeng. 01/2007; 17:76-80.
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ABSTRACT: This paper provides an approach to monitor oscillation status in tunnel diode measurement circuits-by measuring the second derivative of the current-voltage (I-V) characteristic curve while doing I-V curve measurement. The method of using the second derivative to detect oscillations works even when the oscillation frequency is ultrahigh or the oscillation amplitude is very small, e.g., below 10 mV. In this paper, the experimental principle of the tunneling spectroscopy was extended to measurement circuits with the presence of internal oscillations, in contrast to the conventional tunneling spectroscopy, which normally does not deal with internal oscillation. The numerical relationships between the measured average values of transient derivatives and the derivatives of the average current are derived: The average values of the transient first and second derivatives are shown to equal the derivatives of the average current. These relationships serve as the foundation for the authors' experiments. The typical oscillation characteristics in the curves of the first and the second derivatives are used to detect the presence of oscillations and the bias voltage range of oscillation in the I-V curve. The monitor of oscillation status during measurements provides the tester the confidence in the measurement data and whether it is necessary to improve the test circuit further. Finally, benefited from free-of-oscillation, the indirect tunneling current contributions arising by 121-mV (TO+O) two-phonon combination, 144-mV (TA+O+O) and 181-mV (TO+O+O) three-phonon combinations at the negative differential resistance region are observed from a silicon Esaki tunnel diode at 4.2 K
IEEE Transactions on Electron Devices 11/2006; · 2.32 Impact Factor
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ABSTRACT: In AlGaN/GaN heterostructure field-effect transistor structures, the surface defects and dislocations may serve as trapping centers and affect the device performance via leakage current and low-frequency noise. In this paper we report results of our investigation of the trapping characteristics of SiO2-passivated Al0.2Ga0.8N/GaN heterostructure field-effect transistors using the capacitance-voltage (CV) profiling technique. From the measured frequency dependent CV data, we identified the characteristics of the traps at the AlGaN/GaN interface adjoining the channel and on the surface along the ungated region between the gate and drain. Based on the measured data, the influence of the channel traps on the low-frequency noise spectra and the effect of the surface traps on possible leakage noise are analyzed and compared with the previous studies.
Journal of Nanoelectronics and Optoelectronics 07/2006; 1(2):258-263. · 0.56 Impact Factor
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ABSTRACT: We propose and analyze logic circuits utilizing spin waves as a physical mechanism for information transmission and processing. The novelty of this approach is that information transmission is accomplished without charge transfer. A bit of information is encoded into the phase of spin wave propagating in a ferromagnetic film - spin wave bus. The communication between the spin wave bus and outer devices is performed in a wireless manner via a magnetic field. We describe an example of logic device using high frequency transmission lines to excite and detect spin waves. The performance is illustrated by numerical modeling based on the experimental data for spin wave excitation and propagation in NiFe film. We also propose an original scheme for output signal amplification based on the effect of hole-mediated ferromagnetism. Potentially, logic circuits with spin wave bus may be beneficial in terms of power consumption and resolve the interconnect problem. Another expected benefit is in the enhanced logic functionality. It is possible to achieve all advantages of the phase logic using spin waves for information processing. The shortcomings and limitations of circuits with spin wave bus are discussed
Information Technology: New Generations, 2006. ITNG 2006. Third International Conference on; 05/2006
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ABSTRACT: Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C<sub>BC</sub>) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f<sub>T</sub>) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f<sub>max</sub>) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV<sub>CEO</sub>) between 4 and 5.2 V, which are the highest f<sub>T</sub> and the highest f<sub>T</sub>·BV<sub>CEO</sub> product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.
IEEE Transactions on Electron Devices 08/2005; · 2.32 Impact Factor
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ABSTRACT: In the nanoelectronics era with ever smaller devices and higher densities, there are challenges of signal transmission and information communications via interconnects. We examine the interconnect issues for both charge-based and spin-based information systems. For charge-based systems, since there are substantial activities in optical interconnect, this paper focuses on other concepts and approaches. Self-assembled molecular wires, carbon nanotubes/nanowires and virus engineered metallic wires can be used for interconnects. The use of new nano-architectures such as cellular automata, which use mostly nearest neighbors, make the use of self-assembled interconnects even more attractive. These techniques may be applied readily to molecular devices. Spin-based devices offer a new opportunity for low power, high functional throughput applications. We analyze the use of spin waves for information transmission buses referred to as spin wave bus. By introducing these novel circuits built on the spin-based devices and spin wave interconnect, we anticipate enhanced logic functionality. The challenges and issues are discussed.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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ABSTRACT: When voltage is suddenly applied to vertical, parallel dielectric-coated electrodes dipped into a liquid with finite conductivity, the liquid responds by rising up to reach a new hydrostatic equilibrium height. On the microfluidic scale, the dominating mechanism impeding this electromechanically induced actuation appears to be a dynamic friction force that is directly proportional to the velocity of the contact line moving along the solid surface. This mechanism has its origin in the molecular dynamics of the liquid coming into contact with the solid surface. A simple reduced-order model for the rising column of liquid is used to quantify the magnitude of this frictional effect by providing estimates for the contact line friction coefficient. Above some critical threshold of voltage, the electromechanical force is clamped, presumably by the same mechanism responsible for contact angle saturation and previously reported static height-of-rise limits. The important distinction for the dynamic case is that the onset of the saturation effect is delayed in time until the column has risen more than about halfway to its static equilibrium height.
Langmuir 05/2005; 21(9):4211-7. · 4.19 Impact Factor
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ABSTRACT: A novel horizontal current bipolar transistor (HCBT), suitable for the integration with the pillar-like MOSFETs, is processed with the reduced volume of the parasitic regions, achieved by the partial etching of the collector n-hill region and the self-protection of the p<sup>+</sup> extrinsic base from tetramethyl ammonium hydroxide etch-back. The HCBT fabricated by a low-cost technology exhibits the cutoff frequency (f<sub>T</sub>) of 30.4 GHz, the maximum frequency of oscillations (f<sub>max</sub>) of 35GHz and the collector-emitter breakdown voltage (BV<sub>CEO</sub>) of 4.2 V, which are the highest f<sub>T</sub> and the highest f<sub>T</sub>BV<sub>CEO</sub> product among the lateral bipolar transistors (LBTs).
IEEE Electron Device Letters 04/2005; · 2.85 Impact Factor
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ABSTRACT: We propose and analyze a cellular nonlinear network (CNN) based on a semiconductor nanostructure consisting of multiple layers of two semiconductors along with an incorporated quantum dot layer. An elementary logic cell of the proposed CNN consists of two resonant tunneling diodes connected in series through a quantum dot. The cell may be realized with multiple layers of two semiconductor materials with an embedded dot layer in between. The local interconnections of nanocells are achieved via tunneling between the neighboring quantum dots. Cells may be biased by the common column contacts, and only edge cells have individual I/O ports. Using approximate tunneling characteristics, we simulated network dynamics and found procedures leading to useful logic functionality. In order to illustrate network capabilities for image processing, we present examples of filtering, erosion, dilation, and edge detection carried out on a test image on a 400×269 cell template. The realization of a number of logic functions in one module is possible due to the incorporation of nonlinear (tunneling) elements for cell interconnections. The proposed CNN architecture for nanostructures demonstrates powerful computing potential that will be beneficial for many practical applications.
IEEE Transactions on Electron Devices 03/2005; · 2.32 Impact Factor
