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ABSTRACT: Thermal management of Integration Circuit (IC) becomes more and more important with the scaling of CMOS technology and dramatic increase of power density. Performance of thermal management application is highly related to the accuracy of the temperature monitoring devices. However, due to increasing process variations and parameter drifts, temperature measurements by on-chip thermal sensors may not be accurate unless these sensors are calibrated before shipping the devices to the users. Existing calibration methods impose large time cost and cannot be used for in-field calibration. In this paper, we propose a technique to calibrate on-chip thermal sensors during manufacturing as well as in-field. We model the cyclic dependence between leakage power and temperature and perform calibrations to evaluate the calibration accuracy. Experimental results on 100 dies with different process variation parameters and three corner cases show that our technique have very high accuracy.
Quality Electronic Design (ISQED), 2011 12th International Symposium on; 04/2011
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ABSTRACT: Conventional power constrained test scheduling methods do not guarantee a thermal-safe solution. In this paper, we propose a test scheduling algorithm that satisfies the resource, power, and thermal constraints. First, in contrast to existing schemes, the proposed algorithm exploits superposition principle to perform fast and accurate thermal simulation, which, in turn, allows the algorithm to search for solutions which introduce cooling periods between tests to reduce the overall test length. Second, we propose a test partition-based method to further improve the performance of the test scheduling. We apply our test scheduling algorithm to ITC'02 SoC benchmarks and the results show considerable improvement in the total test length over existing methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 03/2011; · 1.27 Impact Factor
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ABSTRACT: Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random "care" bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
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ABSTRACT: For core-based system-on-chip (SoC) testing, conventional power-constrained test scheduling methods do not guarantee a thermal-safe solution. Also, most of the test scheduling schemes make poor assumptions about power consumption. In deep submicron era, leakage power and wake-up power consumption can not be neglected. In this paper, we propose a partition based thermal-aware test scheduling algorithm with more realistic assumptions of recent SoCs. In our test scheduling algorithm, each test is partitioned and the earliest starting time of each partition is searched. To reduce the execution time of thermal simulation, we also exploit superposition principle to compute the power and thermal profile rapidly and accurately. We apply our test scheduling algorithm to ITC'02 SoC benchmarks and the results show improvements in the total test time over scheduling schemes without partitioning.
Asian Test Symposium, 2009. ATS '09.; 12/2009
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ABSTRACT: Calibrating nonlinear mobile sensors in-field is a challenging task due to the unavailability of controlled signal field and pre-calibrated sensor devices. In this paper, we propose a Density Guided blind Calibration (DGC) scheme for nonlinear mobile sensors by approximating the nonlinear calibration functions using piecewise linear functions. The DGC scheme exploits the fact that sensors moving in the same region collect similar fraction of true values in any given interval over time. The proposed scheme tackles the nonlinear calibration problem through an optimization formulation which is very easy to solve. The effectiveness of the proposed scheme is verified through simulations and an experiment with MICA2 light sensors.
Sensor, Mesh and Ad Hoc Communications and Networks, 2009. SECON '09. 6th Annual IEEE Communications Society Conference on; 07/2009
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ABSTRACT: Detection latency, which is defined as the time from the target arrival to the time of the first detection, is an important metric for the performance of sensor networks carrying out target detection, especially when the target is malicious or hostile. It characterizes the efficiency of detecting the presence of a target in a region of interest. Traditionally, stationary sensor networks are used to perform such sensing tasks. Consequently, nearly all research literature for the target detection problem has focused on stationary sensor networks. This paper addresses the problem of detecting the presence/absence of a target using a mobile sensor network. An analytic method is proposed to model the detection latency based on a collaborative sensing architecture. Detection latency for different node mobility models is presented. The accuracy of the analytic model is verified by simulations. This paper also compares the performance of mobile and stationary sensor networks. The comparison shows that if the target is present at the worst possible location in a given deployment, then detection latency of mobile sensor networks is considerably shorter as compared to that of stationary networks with the same number of nodes.
IEEE Transactions on Computers 06/2009; · 1.10 Impact Factor
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ABSTRACT: In-field calibration of sensor devices is known to be a challenging problem because there is often no access to a controlled signal field and/or a pre-calibrated device to provide the ground truth. Nonlinear characteristics of sensor devices make the calibration problem even harder. In this paper, we describe two blind calibration schemes for nonlinear mobile sensor nodes: nullspace based calibration (NBC) and moments based calibration (MBC). Simulation results are included to demonstrate the effectiveness of the proposed schemes. MBC scheme is also used to calibrate light sensors on MICA2 motes in a light field generated by a light bulb. Results show that significant error reduction can be achieved when nonlinearity is considered.
Sensor, Mesh and Ad Hoc Communications and Networks, 2008. SECON '08. 5th Annual IEEE Communications Society Conference on; 07/2008
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X. Wen,
K. Miyase,
S. Kajihara,
H. Furukawa,
Y. Yamato,
A Takashima,
K Noda,
H Ito,
K. Hatayama,
T. Aikyo, K.K. Saluja
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ABSTRACT: Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.
European Test, 2008 13th; 06/2008
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ABSTRACT: In-field calibration of sensor devices is known to be a challenging problem because there is often no access to a controlled signal field and/or a pre-calibrated device to measure the existing signal field. In this paper, we describe a blind calibration scheme that is tailored for sensor networks with mobile nodes. The scheme proposed in this paper exploits the fact that sensor devices are moving in the same region and hence the signal statistics they observe over time are almost the same. Analysis and simulation results are included to demonstrate the effectiveness of the proposed scheme.
Communications, 2008. ICC '08. IEEE International Conference on; 06/2008
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ABSTRACT: Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.
Asian Test Symposium, 2007. ATS '07. 16th; 11/2007
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ABSTRACT: X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effectiveness of previous X-filling methods suffers from lack of guidance in selecting targets and values for X-filling. This paper addresses this problem with a highly-guided X-filling method based on two novel concepts: (1) X-score for X-filling target selection and (2) probabilistic weighted capture transition count for Y-filling value selection. Experimental results show the superiority of the new X-filling method for capture power reduction.
Computer Design, 2006. ICCD 2006. International Conference on; 11/2007
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ABSTRACT: Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2007; · 1.22 Impact Factor
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ABSTRACT: IR-drop-induced malfunction is mostly caused by timing violations on activated critical paths during the capture cycle of at-speed scan testing. A critical-path-aware X-filling method is proposed for reducing IR-drop, especially on gates that are close to activated critical paths, thus effectively preventing test-induced yield loss.
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE; 07/2007
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ABSTRACT: Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored. The compaction of diagnostic test vectors must take care of all fault pairs that need to be distinguished by a given test vector set. Clearly, the number of fault pairs is much larger than the number of faults thus making this problem very difficult and challenging. The key contributions of this paper are: 1) to use techniques for reducing the size of fault pairs to be considered at a time, 2) to use novel variants of the fault distinguishing table method for combinational circuits and reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits. Finally, the experimental results for ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed methods
Design Automation, 2006. Asia and South Pacific Conference on; 02/2006
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ABSTRACT: The random access scan (RAS) has the ability to address major problems associated with serial-scan method. A practically implementable RAS test architecture called progressive random access scan (PRAS) was introduced earlier. This paper proposes a generalized architecture for the PRAS. We show that the generalized PRAS architecture offers two orders of magnitude gains in test application time over traditional serial scan and is superior to multiple serial scan in terms of the use of tester channels.
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on; 02/2006
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ABSTRACT: Testing of VLSI circuits is challenged by the increasing volume of test data that adds constraints on tester memory and impacts test application time substantially. Space compactors are commonly used to reduce the test volume by one or two orders of magnitude. However, such level of compaction reduces the quality of the diagnostic of faults because it is difficult to identify the locations of errors in the compacted response. In this paper, we introduce a design of space compactors that can be used in pass/fail mode as well as in diagnostic mode with enhanced performance by trading off compaction ratio for diagnostic ability. We analyze the properties of the compactors and evaluate their performance through simulations.
Test Symposium, 2005. Proceedings. 14th Asian; 01/2006
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ABSTRACT: Three issues that are dominating test research today are test application time, test data volume and test power. Researchers have focused on these issues mostly considering the popular serial scan architecture for its relatively low hardware overhead while ignoring the fact that exponential drop in hardware cost offers opportunities for implementing a test architecture that previously may have been un-acceptable. This paper takes such a paradigm shift into account and studies the simultaneous solution of all three problems of serial scan by making use of progressive random access scan test architecture. This architecture only increases the hardware cost marginally while providing marked improvements for the three issues. This paper explains the test architecture and then develops a test generation methodology which reduces the test application time by nearly 75%, test data volume by 50% for the benchmark circuits. Above all, the architecture is inherently so efficient that it reduces the test power by nearly 99% or more of the test power consumption compared to serial scan.
Test Symposium, 2005. Proceedings. 14th Asian; 01/2006
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ABSTRACT: Traditional testing research for testing VLSI circuits has been confined to the use of serial scan test architecture whose origin lies in keeping the hardware overhead low. However, there has been a paradigm shift in the cost factor - the transistor cost has been dropping exponentially whereas the test cost is starting to increase. We believe that adding marginally more hardware is acceptable provided the test cost can be reduced considerably. This paper takes such a view of testing and rejuvenates the random access scan as a design for testability method that simultaneously addresses three limitations of the traditional serial scan namely, test data volume, test application time, and test power. The novelty of the progressive random access scan approach proposed in this paper lies in developing the test architecture and formulating the test application time and test data volume reduction problems. We provide a traveling salesman formulation of these problems in our test architecture setting. Experimental results show the practicality of our approach as the hardware cost components, consisting of routing and transistor count, increase only marginally compared to the serial scan approach whereas there is a dramatic decrease in test power consumption (nearly a 1000 fold decrease in average test power) as well as the test data volume and the test times are halved
Test Conference, 2005. Proceedings. ITC 2005. IEEE International; 12/2005
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ABSTRACT: Occurrence of unknown values in scan chains in response to test vectors is a common phenomenon. This paper presents a method for designing matrices for linear test output compactors by using rows of multiple weights. Compared to previously proposed compactors, the method reduces the masking caused by unknowns by an order of magnitude provided that the unknowns are non-uniformally distributed among the scan chains. Also, using multiple rather than single weight compactors increases the compaction ratio and reduces the hardware overhead. The effectiveness of multiple weight compactors is demonstrated through analysis, simulations and experiments with test response from an industrial design.
Test Conference, 2005. Proceedings. ITC 2005. IEEE International; 12/2005
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ABSTRACT: Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0's and 1's to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield loss
Test Conference, 2005. Proceedings. ITC 2005. IEEE International; 12/2005
