J. M. McGarrity

Army Research Laboratory, Adelphi, MD, USA

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Publications (32)35.14 Total impact

  • Article: A Physical Model of High Temperature 4H-SiC MOSFETs
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    ABSTRACT: A comprehensive physical model for the analysis, characterization, and design of 4H-silicon carbide (SiC) MOSFETs has been developed. The model has been verified for an extensive range of bias conditions and temperatures. It incorporates details of interface trap densities, Coulombic interface trap scattering, surface roughness scattering, phonon scattering, velocity saturation, and their dependences on bias and temperature. The physics-based models were implemented into our device simulator that is tailored for 4H-SiC MOSFET analysis. By using a methodology of numerical modeling, simulation, and close correlation with experimental data, values for various physical parameters governing the operation of 4H-SiC MOSFETs, including the temperature-dependent interface trap density of states, the root-mean-square height and correlation length of the surface roughness, and the electron saturation velocity in the channel and its dependence on temperature, have been extracted. Coulomb scattering and surface roughness scattering limit surface mobility for a wide range of temperatures in the subthreshold and linear regions of device operation, whereas the saturation velocity and the high-field mobility limit current in the saturation region.
    IEEE Transactions on Electron Devices 09/2008; · 2.32 Impact Factor
  • Conference Proceeding: Electron Transport at Technologically Significant Stepped 4H-SiC/SiO2 Interfaces
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    ABSTRACT: The impact of interface steps on electron transport in 4H-SiC MOSFETs is investigated. Steps are found to cause a large increase in roughness scattering leading to anisotropy in the low-field mobility. An increase in phonon scattering, due to variations in the channel depth, is also predicted. Monte Carlo transport simulations show that interface steps lead to degradation of the high-field phonon-limited mobility. Results are important considering the technological significance of 4H-SiC in high temperature, high power electronics
    Simulation of Semiconductor Processes and Devices, 2006 International Conference on; 10/2006
  • Conference Proceeding: Characterization of 4H-SiC MOSFET Interface Trap Charge Density Using a First Principles Coulomb Scattering Mobility Model and Device Simulation
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    ABSTRACT: We have developed a physics based device simulator for detailed numerical analysis of 4H-SiC MOSFETs. As part of the drift diffusion model implemented in the simulator, a first principles quasi-2D Coulomb scattering mobility model for SiC MOSFETs has been developed. This Coulomb scattering mobility model takes into account scattering by occupied interface traps, scattering by fixed oxide charges, distribution of mobile carriers inside the inversion layer, screening by mobile carriers and temperature. Using this mobility model it has been shown that Coulomb scattering plays a dominant role very close to the interface. The interface trap density of states profile has been extracted by comparing simulated I-V curves to experimental data for room temperature. Simulations show that interface trap density of states is low in the midgap region and very high near the conduction band edge in 4H SiC, and it severely limits device performance.
    Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on; 10/2005
  • Conference Proceeding: Impact of Surface Steps on the Roughness Mobility in 4H-SiC
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    ABSTRACT: In this work, the step distributions are used to generate surface morphologies via Monte Carlo methods. Steps propagate along the [112macr0] direction. In addition to the stepped surface, a random surface roughness is added along both the [112macr0] (perpendicular to steps) and [11macr00] (parallel to steps) directions. The rms height Delta=0.38nm and correlation length L=2.2nm of the random contribution correspond to typical values in Si scaled to account for the unit cell dimensions of SiC
    Semiconductor Device Research Symposium, 2005 International; 02/2005
  • Conference Proceeding: Numerical and experimental characterization of 4H-SiC Schottky diodes
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    ABSTRACT: In this paper, experiment and simulation on n-type Ti/4H SiC Schottky diodes were performed. I-V measurements for 4H-SiC Schottky diodes under different temperatures were performed in an ITS8000 testing system. The combined use of the device simulator and experiments to extract key physical parameters, including temperature dependent mobility, and Schottky barrier height.
    Semiconductor Device Research Symposium, 2003 International; 01/2004
  • Conference Proceeding: Investigation of temperature effects on electron transport in SiCusing unique full band Monte Carlo simulation
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    ABSTRACT: We present a detailed full band Monte Carlo (MC) study of electron transport in 6H-SiC ⊥ to the c-axis with emphasis on the effect of temperature and the band structure at high fields. The empirical pseudopotential for 6H-SiC is used for the first time in the MC transport simulations. We find that as many as five conduction bands and the Γ valley make significant contributions to electron transport at high temperature and fields. Electron-phonon coupling constants are obtained for 6H-SiC by fitting to experimental temperature-dependent drift velocity for the first time
    Semiconductor Device Research Symposium, 2001 International; 02/2001
  • Conference Proceeding: A physics-based empirical pseudopotential model for calculating band structures of simple and complex semiconductors
    G. Pennington, N. Goldsman, J.M. McGarrity, F. Crowne
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    ABSTRACT: The full zone band structure is often needed for adequate simulation of semiconductor devices. It is important for devices operating under high power and high fields and determines many material properties. The computational ease and good accuracy of the empirical pseudopotential method (EPM) make it the band structure method of choice for full-zone simulations. While the EPM works well for most diamond and zincblende semiconductors, it becomes less effective for more complicated structures with larger unit cells. For these materials, more EPM parameters must be fitted while less experimental data is usually available. Through the adaption of the nonlocal atomic model potential of Heine and Animalu (Phil. Mag. vol. 12, pp. 1249-1269, 1965), we have developed a model empirical pseudopotential which, by drastically reducing the fitting parameters needed, can extend the use of the EPM to semiconductors with large unit cells. The method is effectively applied to the band structure calculations of Si, C, 3C-SiC, 4H-SiC, and 6H-SiC here
    Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on; 02/2000
  • Article: An overview of radiation-induced interface traps in MOS structures
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    ABSTRACT: The authors focus on radiation-induced interface traps, describing first how they fit into the overall radiation response of metal-oxide-semiconductor structures. Detailed measurements of the time, field and temperature dependences of the build-up of radiation-induced interface traps indicate three processes by which the build-up occurs. The largest of these is the slow two-stage process described by McLean and co-workers (1989) which is rate-limited by the hopping transport of hydrogen ions. Two other faster processes also contribute small interface trap build-ups in gate oxides. The processes seem to be controlled by hole transport to the Si/SiO2 interface and by neutral hydrogen diffusion respectively. They also discuss several models which fall into three classes, corresponding roughly to the three processes observed experimentally. Other topics discussed briefly are dose dependence, field oxide effects, chemical and processing dependences and scaling effects.
    Semiconductor Science and Technology 12/1998; 4(12):986. · 1.72 Impact Factor
  • Conference Proceeding: Effects of interface-trapped charge on the SiC MOSFET characteristics
    C.J. Scozzi, J.M. McGarrity
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    ABSTRACT: High quality SiC/SiO<sub>2</sub> interfaces are critical to the development of silicon carbide power MOSFETs, IGBTs, and MOS-controlled thyristors. In this work, we examine the effects of thermal stress on the SiC/SiO<sub>2</sub> interface of n-channel MOSFETs that had gate oxides formed by low-pressure chemical-vapor deposition on the silicon face of a 6H-SiC epitaxial layer with subsequent re-oxidation to improve the interface. These devices were found to have a pre-stress mean interface-trap density of 5×10<sup>11</sup> cm<sup>-2</sup> eV<sup>-1</sup> at room temperature. The interface-trap density for these oxides was shown to be significantly increased by applying moderate stress (2 MV/cm) at 300°C. The post-stress change in device characteristics is shown to be consistent with the stress-induced increase in interface traps
    High Temperature Electronics Conference, 1998. HITEC. 1998 Fourth International; 07/1998
  • Article: Modeling the temperature response of 4H silicon carbide junction field-effect transistors
    C. J. Scozzie, F. B. McLean, J. M. McGarrity
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    ABSTRACT: The electrical characteristics of 4H-SiC depletion-mode junction field-effect transistors (JFETs) have been measured over an extended temperature range from 218 to 673 K. A basic model has been applied to predict I–V characteristics for SiC JFETs over this extended temperature range using the standard abrupt-junction long-channel JFET equations. The model employs a two-level donor ionization structure using ionization energies of 0.050 and 0.080 eV and assumes a two-step inverse power law dependence of mobility on temperature based on recently published Hall measurement data. The modeled I–V characteristics are in good agreement with the experimental data over the temperature range from 273 to 673 K. The deviations between the experimental data and the response model at the temperature extremes are attributed to increased substrate resistivity at 218 K and increased device leakage currents at 673 K.
    Journal of Applied Physics. 05/1997; 81(11):7687-7689.
  • Article: Silicon carbide FETs for high temperature nuclear environments
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    ABSTRACT: SiC transistors can operate at very high temperatures and survive very high radiation doses. These characteristics make SiC potentially the ideal technology for nuclear power applications. In this paper we report, for the first time, on the active in-core irradiation of 6H-SiC depletion-mode junction field-effect transistors (IFETs) at 25° and 300°C in a nuclear reactor operated at 200 kW. No significant degradation in the device characteristics was observed until the total neutron fluence exceeded 10<sup>15</sup> n/cm<sup>2</sup> for irradiation at 25°C, and no significant changes were observed even at 5×10<sup>15</sup> n/cm<sup>2</sup> at 300°C. The results of this experiment may also indicate exciting evidence for the anneal of neutron displacement damage for devices irradiated at 300°C
    IEEE Transactions on Nuclear Science 07/1996; · 1.45 Impact Factor
  • Article: Modeling the electrical characteristics of n‐channel 6H–SiC junction‐field‐effect transistors as a function of temperature
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    ABSTRACT: The electrical characteristics of buried‐gate, n‐channel junction‐field‐effect transistors (JFETs) fabricated in epitaxial layers grown on 6H–SiC wafers have been measured as a function of temperature, from 218 to 773 K (-55 to 500 °C). The data are in good agreement with predictions of a model that uses standard abrupt‐junction, long‐channel JFET device equations for which the carrier concentration is calculated based on a two‐level ionization structure for the nitrogen donor. An inverse power‐law dependence of carrier mobility on temperature is assumed based on recent measurements of Hall mobility in epitaxial films of comparable doping. The only free parameter of the model is the compensation density, which is chosen by fitting the calculated saturated drain current to the measured value at room temperature. There are some deviations between the calculated and measured I–V characteristics at both temperature extremes (218 and 773 K), which are attributed to increased substrate resistivity at 218 K and to increased gate leakage current at 773 K.
    Journal of Applied Physics 02/1996; · 2.17 Impact Factor
  • Conference Proceeding: High temperature silicon carbide FETs for radiation environments
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    ABSTRACT: Silicon carbide (SiC) is a very promising semiconductor material for the development of electronics that will operate at high temperature; it has the additional advantage that for some applications it should be less sensitive to radiation than Si or GaAs. There will be advantages to eventually using SiC to build very radiation-resistant, high-temperature circuits, which could be located near or within severe radiation environments. System benefits would come from development of circuits with sensor amplifier/multiplexer and control signal demultiplexer/motor drive electronics functions. The goal of our research is ultimately to demonstrate that high-temperature radiation-hardened circuits can be built to meet the kinds of needs discussed above, In this paper we report on the operation of state of the art SiC JFETs over a wide temperature range and in severe radiation environments. These devices represent the current state of the art but do not represent the limits of operation of SiC semiconductor devices. This work was in fact carried out to increase our understanding of the device characteristics so as to allow the design of new SiC circuits which could meet the extremely stressful requirements of nuclear power systems
    Nuclear Science Symposium and Medical Imaging Conference Record, 1995., 1995 IEEE; 11/1995
  • Article: Analysis of neutron damage in high-temperature silicon carbide JFETs
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    ABSTRACT: Neutron-induced displacement damage effects in n-channel, depletion-mode junction-field-effect transistors (JFETs) fabricated on 6H-silicon carbide are reported as a function of temperature from room temperature (RT) to 300/spl deg/C. The data are analyzed in terms of a refined model that folds in recently reported information on the two-level ionization energy structure of the nitrogen donors. A value of 5/spl plusmn/1 cm/sup -3/ per n/cm/sup 2/ is obtained for the deep-level defect introduction rate induced by the neutron irradiation. Due to partial ionization of the donor atoms at RT, the carrier removal rate is a function of temperature, varying from 3.5 cm/sup -1/ at RT to 4.75 cm/sup -1/ at 300/spl deg/C. The relative neutron effect on carrier mobility varies with temperature approximately as T/sup -7/2/, dropping by an order of magnitude at 300/spl deg/C compared with the RT effect. The results offer further support for the use of SiC devices in applications which combine high-temperature and severe radiation environments, where the use of Si and GaAs technologies is limited.< >
    IEEE Transactions on Nuclear Science 01/1995; · 1.45 Impact Factor
  • Conference Proceeding: High temperature stressing of SiC JFETs at 300/spl deg/C
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    ABSTRACT: Silicon carbide is an important emerging semiconductor technology for high power and high temperature applications. Although many papers in the literature report some of the characteristics and advantages of various SiC devices, very little information is available on the test and operation of these devices for an extended period of time. For our study a special lot of SiC JFETs was fabricated and packaged by CREE Research Inc. These devices were delivered to the Army Research Laboratory where they have been electrically characterized, radiation tested and, as reported here, subjected to thermal stress at 300/spl deg/C for 1000 hours under various bias conditions.< >
    Reliability Physics Symposium, 1994. 32nd Annual Proceedings., IEEE International; 05/1994
  • Article: Silicon carbide JFET radiation response
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    ABSTRACT: Total dose and neutron-induced displacement damage effect studies are reported for n-channel, 2-μm channel length, depletion mode junction-field-effect-transistors (JFETs) fabricated on 6H-silicon carbide. Very little effect was observed on device characteristics for total dose ionizing radiation for doses up to 100 Mrads(Si), but the devices were significantly degraded after a neutron fluence of 10<sup>16 </sup> n/cm<sup>2</sup>. A value of 4.5±0.5 carriers/cm<sup>3 </sup>/neutrons/cm was obtained for the carrier removal rate from neutron irradiation. The results offer promise for SiC devices to be used in applications which combine high-temperature and radiation environments, where the use of Si and GaAs technologies is limited
    IEEE Transactions on Nuclear Science 01/1993; · 1.45 Impact Factor
  • Article: Neutron irradiation effects on PZT thin films for nonvolatile-memory applications
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    ABSTRACT: The authors examine the effects of neutron irradiation on ferroelectric (FE) lead-zirconate-titanate (PZT) thin films. The data show only a slight loss in the FE switched charge, as measured by the hysteresis loops, up to 1×10<sup>15</sup> n/m<sup>2</sup>. The retained polarization, as measured by a pulse technique, showed a larger loss of remanent polarization which saturated at the lowest fluence measured (1×10<sup>13</sup> n/cm<sup>2</sup>). However, in neither case does it appear that the film was degraded sufficiently to cause devices made from sol-gel PZT to fail at fluences at or below 1×10 <sup>15</sup> n/cm<sup>2</sup>. The endurance characteristics of the film were unchanged due to neutron irradiation
    IEEE Transactions on Nuclear Science 01/1992; · 1.45 Impact Factor
  • Article: Radiation evaluation of commercial ferroelectric nonvolatile memories
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    ABSTRACT: Ferroelectric (FE) on complementary metal-oxide-semiconductor (CMOS) 4-bit nonvolatile memories, 8-bit octal latches (with and without FE), and process control test chips were used to establish a baseline characterization of the radiation response of CMOS/FE integrated devices and to determine whether the additional FE processing caused significant degradation to the baseline CMOS process. Functional failure of all 4-bit memories and octal latches occurred at total doses of between 2 and 4 krad(Si), most likely due to field-oxide effects in the underlying CMOS. No significant difference was observed between the radiation response of devices with and without the FE film in this commercial process
    IEEE Transactions on Nuclear Science 01/1992; · 1.45 Impact Factor
  • Article: Post-Irradiation Effects in Field-Oxide Isolation Structures
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    ABSTRACT: We have studied experimentally the time dependence of leakage currents in six CMOS (complementary metaloxide semiconductor) processes using LOCOS (local oxidation of silicon) isolation structures. These six process lines represent six different U. S. semiconductor companies. In their radiation response, these processes range from very hard to very soft. In the softer processes, the radiation-induced leakage currents are due to the turning on of a leakage path either under the thick field-oxide or along the transistor edge (bird's beak) region. In the hardest process, the field-oxide did not turn on, and the leakage was entirely due to subthreshold current in the gate region. These different mechanisms have qualitatively different time dependences, which we describe and discuss. We also discuss the implications of our results for hardness assurance testing.
    IEEE Transactions on Nuclear Science 01/1988; · 1.45 Impact Factor
  • Article: Saturation of Threshold Voltage Shift in MOSFET's at High Total Dose
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    ABSTRACT: We present the results of an investigation into the buildup of trapped positive oxide charge responsible for a negative component of radiation-induced threshold voltage shift in both hard and soft metaloxide semiconductor (MOS) gate oxides and the processes which limit this buildup. Hole-trapping effects at doses to 15 Mrad(SiO2) were examined in MOS field-effect transistors (MOSFET's) and MOS capacitors with 11- to 27-nm gate oxides. The observed saturation of threshold voltage shift was modeled with the aid of a computer simulation of charge buildup in an MOS structure and was found to be caused by a complex interaction between trap filling and recombination of radiation-generated free electrons with trapped holes, modulated by trapped-hole-induced distortion of the oxide electric field. A supplemental measurement of 10-keV x-ray-induced currents in MOS capacitors produced no evidence for radiation-generated hot electron injection from the Si substrate into SiO2 layers of various thicknesses and also yielded data on x-ray-induced charge generation in the SiO2.
    IEEE Transactions on Nuclear Science 01/1987; · 1.45 Impact Factor