C.L. Keast

Massachusetts Institute of Technology, Cambridge, Massachusetts, United States

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Publications (69)57.61 Total impact

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    ABSTRACT: This paper reports on the successful demonstration of radio frequency (RF) components in support of an integrated wide band/high dynamic range X-band receiver in 180-nm fully-depleted (FD) SOI CMOS technology. The demonstrated microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier (LNA), Marchand balun, balanced amplifiers, double balanced mixer, non-reflective filter, and an IF amplifier. The X-band receiver front end module yielded a gain of 13.5-15 dB, 5.2-5.8 dB noise figure (NF), across the frequency band (3.7-4.3 GHz).
    2012 IEEE International SOI Conference; 10/2012
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    ABSTRACT: This paper describes a wide band/high dynamic range receiver implemented in a 0.18-μm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The system demonstration is a single conversion architecture with RF input at X-Band and IF output at S-Band. The receiver yielded 20-21.5 dB conversion gain, 5.6-6 dB noise figure, and 16.7 dBm OIP3 across a 600-MHz instantaneous bandwidth at S-Band operation.
    Ultra-Wideband (ICUWB), 2012 IEEE International Conference on; 01/2012
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    ABSTRACT: The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces D <sub>it</sub>. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction in C <sub>gd</sub>, and 55% reduction in V<sub>t</sub> variation when compared with conventional transistors, although significant short-channel effects are observed.
    IEEE Transactions on Electron Devices 03/2011; · 2.36 Impact Factor
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    ABSTRACT: A workfunction-tuned TiN metal gate is integrated into ultra-low-power FDSOI CMOS transistors, optimized for subthreshold operation at 0.3 V. The workfunction of the TiN metal gate is tunable across the mid-gap range, by adjusting deposition parameters and post-deposition annealing. The transistors show 71% reduction in C<sub>gd</sub> and 55% reduction in V<sub>t</sub> variation, compared to conventional FDSOI transistors of the same size. A 59% decrease in switching energy and a 91% decrease in stage delay is demonstrated in ring oscillators fabricated with the subthreshold-optimized FDSOI transistors when compared to commercial bulk silicon devices.
    SOI Conference (SOI), 2010 IEEE International; 11/2010
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    ABSTRACT: The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the f<sub>max</sub> of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.
    IEEE Microwave and Wireless Components Letters 06/2010; · 2.24 Impact Factor
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    ABSTRACT: Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.
    Proceedings of the IEEE 03/2010; · 5.47 Impact Factor
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    ABSTRACT: It has been shown that few-layer graphene films can be grown by atmospheric chemical vapor deposition using deposited Ni thin films on SiO(2)/Si substrates. In this paper we report the correlation between the thickness variations of the graphene film with the grain size of the Ni film. Further investigations were carried out to increase the grain size of a polycrystalline nickel film. It was found that the minimization of the internal stress not only promotes the growth of the grains with (111) orientation in the Ni film, but it also increases their grain size. Different types of SiO(2) substrates also affect the grain size development. Based upon these observations, an annealing method was used to promote large grain growth while maintaining the continuity of the nickel film. Graphene films grown from Ni films with large versus small grains were compared for confirmation.
    Nanotechnology 01/2010; 21(1):015601. · 3.67 Impact Factor
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    ABSTRACT: Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose. This is because radiation causes charge to be trapped in the buried oxide, and reduces the p-channel FET drive current. When the p-channel FET drive current is reduced, the time required to restore the output of the laser-probed FET back to its original condition is increased, i.e. the upset transient width is increased. A widening of the transient pulse is also observed when a positive bias is applied to the wafer without any exposure to radiation. This is because a positive wafer bias reproduces the shifts in FET threshold voltages that occur during total dose irradiation. Results were also verified with heavy ion testing and mixed mode simulations.
    IEEE Transactions on Nuclear Science 01/2010; · 1.46 Impact Factor
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    ABSTRACT: We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a 40% size reduction to 1.0 μm and with an associated exclusion zone reduced by a factor of 2, substantially smaller than in bulk-Si 3D through-silicon-via (TSV) approaches. These significant enhancements were demonstrated with our 3D technology based on conventional SOI wafers.
    01/2010;
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    ABSTRACT: Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.
    SOI Conference, 2009 IEEE International; 11/2009
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    ABSTRACT: We characterized TID effects in MITLL 3DIC technology. We found that the effects were comparable for nFETs on the bottom tier with that on single tier wafers. Less positive charge build-up is observed for wide nFETs on the upper tiers, and this is due to the absence of silicon below the BOX. Other results indicate that MITLL 3DIC technology can be hardened to ionizing radiation by modifying the BOX.
    SOI Conference, 2009 IEEE International; 11/2009
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    ABSTRACT: In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 times 1024 diode array with 8-mum pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
    3D System Integration, 2009. 3DIC 2009. IEEE International Conference on; 10/2009
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    ABSTRACT: Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO<sub>2</sub> substrate. The properties and integration of these graphene-on-insulator transistors are presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.
    IEEE Electron Device Letters 08/2009; · 3.02 Impact Factor
  • 06/2009: pages 171-196;
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    ABSTRACT: RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved.
    Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on; 02/2009
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    ABSTRACT: pgouker@ll.mit.edu (781-981-0460) MITLL has developed a three dimensional integrated circuit (3DIC) technology that exploits the advantages of SOI technology to enable wafer stacking and micrometer-scale vertical interconnection of fully fabricated circuit wafers [1,2]. This paper presents the first radiation test results on this 3DIC technology. 3D fabrication process Devices and circuits are fabricated by transferring and interconnecting fully fabricated 150-mm SOI substrates to a base wafer, also a fully fabricated 150-mm SOI substrate. Wafer-level integration is enabled by bonding oxide films at low temperature. High circuit density is enabled by fabricating 3D-vias to interconnect the different tiers. Figure 1 shows a cross-section scanning electron micrograph of a 3DIC wafer showing three FDSOI CMOS tiers, eleven metal layers, and 3D vias interconnecting tiers 1, 2 and 3. On tiers 2 and 3, FETs are inverted so that front gates are below the SOI , the BOX is above the SOI, and the original silicon substrate was removed and replaced by deposited oxides. Figure 1: Scanning Electron Micrographs of a 3DIC wafer with three FDSOI CMOS tiers, eleven metal interconnect layers, and 3D vias interconnecting tiers 1,2 and 3. The dashed lines were drawn to mark the oxide-oxide bonding interface. Description of the experiment Total ionizing dose (TID) effects were characterized using an Aracor 4100, which produces 10-keV X-rays. FDSOI MOSFETs and multiplier circuits were biased during irradiation and characterized before and after dose increments up to a total dose of 2 Mrad (SiO 2). We characterized n-channel MOSFETs (nFETs) fabricated on each tier of 3D wafers, each wafer fabricated on MITLL 0.18-μm FDSOI CMOS process. The process features a 45-nm-thick SOI, 400-nm-thick BOX, 4.2-nm-thick gate oxide, a mesa isolation, cobalt silicided source/drain/polysilicon gate, and three metal levels [3]. 10-keV X-rays are not attenuated when penetrating through the 20-μm-thick oxide layers down to the bottom FETs on tier 1. Radiation test results When exposed to ionizing radiation, MITLL FDSOI FETs degrade because of radiation-induced positive charges trapped in the BOX [4]. The gate and mesa oxides are both thin enough (4.2-nm) that holes generated by the radiation tunnel through them, and don't get trapped. The positive charges trapped in the BOX cause the nFET (pFET) threshold voltage (V t) to decrease (increase) because the SOI body is fully depleted, and the BOX is capacitively coupled to the front gate. A decrease in V t causes an increase in nFET leakage current, which can yield to circuit parametric failure, or even permanent damage.
    01/2009;
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    ABSTRACT: Single event transients were characterized experimentally in fast logic circuits fabricated in 0.18-mum FDSOI CMOS process using laser-probing techniques. We show that the transient pulse widens as it propagates; the widening is largely eliminated by the body contact. Good agreement is observed between pulsed-laser and heavy ion testing.
    IEEE Transactions on Nuclear Science 01/2009; · 1.46 Impact Factor
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    ABSTRACT: Etching of TiN metal gate materials as a part of an integrated flow to fabricate fully depleted silicon-on-insulator ultralow-power transistors is reported. TiN etching is characterized as a function of source power, bias power, gas composition, and substrate temperature in a high density inductively coupled plasma reactor. Under the conditions used in this work, the TiN etch rate appears to be ion flux limited and exhibits a low ion enhanced etching activation energy of 0.033 eV. Notching of the polysilicon layer above the TiN may occur during the polysilicon overetch step as well as the TiN overetch step. Notching is not significantly affected by charging of the underlying gate dielectric under the conditions used. By optimizing the plasma etch process conditions, TiN:SiO2 selectivity of nearly 1000:1 is achieved, and a two-step TiN main etch and TiN overetch process yields well-defined metal gate structures without severe gate profile artifacts.
    Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 01/2009; 27(6):2472-2479. · 1.36 Impact Factor
  • Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, 11/2008: pages 575 - 582; , ISBN: 9783527623051
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    ABSTRACT: The 45nm technology node is witnessing the introduction of high-k dielectric and metal gate materials into CMOS logic production, after about a decade of materials research and process development. Coincidentally, the emerging field of ultra-low power electronics is investigating the integration of metal gate materials with a completely different set of performance needs than those of high-performance CMOS logic. A discussion of the physical and electrical requirements of the gate materials for these two technologies will be presented, along with an introduction to the gate first vs. gate last integration approaches. A key challenge of integrating high-k / metal gates is the plasma etching of the gate stack. Results from etching of dual work function band-edge CMOS logic gates will be presented, demonstrating the feasibility of gate first integration. Plasma etching results on blanket and patterned mid-gap metal gate stacks will also be presented, illustrating how the fundamentals of plasma chemistry and ion-enhanced etching can be used to develop new plasma processes enabling integration of novel gate stack materials. *This work was sponsored by the Air Force under contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the United States Government.
    2008 AIChE Annual Meeting; 11/2008