[Show abstract][Hide abstract] ABSTRACT: Adding low-cost front-end processing to a passive interposer process flow enables the low-cost processing of diodes, SCRs and bipolar transistors. Using those devices in an ESD protection design allows moving a large part of the ESD protection from the stacked die to the interposer.
[Show abstract][Hide abstract] ABSTRACT: In this work the mechanical stress induced in 3D stacks by different packaging process steps is studied. The 3D stacks used in this work are assembled using two identical dies containing a number of stress sensors which are designed and manufactured in 65nm technology. It is observed that the contribution of the package substrate and the die-attach process to the redistribution of mechanical stress inside the 3D stacked IC is more significant than the one of the EMC and that the influence of packaging on the shape and amplitude of local stress around the inter-die interconnects (micro-bumps) is not significant. These observations are supported by the measurements of stress done using micro-Raman spectroscopy and are correlated with the results of finite element modeling and with optical warpage measurements of different packaging configurations.
Proceedings - Electronic Components and Technology Conference 07/2015; 2015:354-361. DOI:10.1109/ECTC.2015.7159617
[Show abstract][Hide abstract] ABSTRACT: Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners ('donut TSVs') and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.
[Show abstract][Hide abstract] ABSTRACT: In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, thermal finite element and compact models are experimentally validated using a dedicated power map with multiple heat sources. Finally, the 3D test package is used to emulate the thermal behavior of a packaged memory-on-logic stack and to assess the thermal interaction between the chips.
Proceedings - Electronic Components and Technology Conference 07/2015; 2015:1134-1141. DOI:10.1109/ECTC.2015.7159737
[Show abstract][Hide abstract] ABSTRACT: Adding functionality to a passive Si interposer used in 2.5/3D integration, can result in system cost reductions. In this work, active components (diodes, BJT, ...) have been integrated on Si interposer using a new low-mask process flow. This low-cost process enables: (1) to move part of the area hungry ESD protection from the stacked dies to the interposer; (2) the realization of pre-bond testable interposers (DFT); and (3) components for analog circuits (diodes, npn, SCR, resistor).
[Show abstract][Hide abstract] ABSTRACT: High speed TSV signals can penetrate through the dielectric liner material, transfer in the silicon substrate and degrade the performance of FEOL devices. In this paper we investigate TSV noise coupling to active device including both FinFET and planar transistors. Calibrated TCAD models are used to perform time domain analysis and understand the mechanisms of substrate noise interaction with active device. Parametric simulations are performed in order to understand the tradeoffs among different design parameters. The results demonstrate superior substrate noise immunity of FinFETs over equivalent planar transistors. In addition we show that a scaled TSV diameter, a novel TSV architecture with thick polymer liner, placing the substrate contact closer to active device and a TSV guard ring helps to mitigate the TSV noise. Finally the importance of electromagnetic coupling effects on Keep Out Zone (KOZ) extraction is illustrated.
2015 International Conference on IC Design & Technology (ICICDT); 06/2015
[Show abstract][Hide abstract] ABSTRACT: Copper plasticity effects in TSV middle and backside TSV last integration flows are analyzed using an advanced 3D TCAD simulator with model parameters calibrated to match experimental data. In this work, a low thermal budget TSV last integration flow is considered. In contrast to the TSV middle flow, the TSV last flow studied here exhibits insignificant TSV pumping, M1 metal thinning or M1 metal resistance increase. The difference in residual stress profiles in BEOL structure for TSV middle and TSV last processes indicates that the process sequence must be optimized in order to minimize the reliability risks. The mobility change in active silicon for the TSV last process is lower as compared to that for the TSV middle process at room temperature due to the lower temperature excursions during the TSV last integration. This study demonstrates that the TSV integration flow must be designed and selected carefully to meet specific performance and reliability requirements.
[Show abstract][Hide abstract] ABSTRACT: Evaluating the importance of electromagnetic (EM) coupling from through silicon vias (TSVs) has become crucial to the design of three-dimensional integrated circuits (3D-ICs). One of the most important parasitic contributions to signal propagation in 3D-ICs is the TSV capacitance. It is both frequency and bias dependent since a TSV is a metal-oxide-semiconductor (MOS) structure. In this work, anomalous TSV capacitance behavior after wafer thinning is reported and investigated by combining measurements and finite element (FEM) semiconductor simulations. Excellent agreement between models and experimental data confirms the origin of the anomalous TSV capacitance behavior: the presence of fixed charges in the back side (BS) passivation layer of the TSV after wafer thinning. In addition, a BS inversion layer can act as a conductive channel between neighboring vias, increasing the capacitive coupling between TSVs. Calibrated equivalent circuit models of the TSV in contact with a BS inversion layer are proposed for the first time in the context of 3D integration and validated.
[Show abstract][Hide abstract] ABSTRACT: CBCM measurements require known clock frequency. We proposed CBCM test structures with an internal start-stop self-pulsing circuit instead of external clock monitoring. The circuit creates 213 pulses in a time-slot defined by SMU pulsed signal, resulting in known clock frequency. We accurately extract MOSFET's gate capacitances of several tens of fF.
[Show abstract][Hide abstract] ABSTRACT: We have successfully developed the new design of MOSFET array structure with high accuracy measurement both for Ion excluding IR drop and Ioff without contamination. We propose measurement algorithm 'feedback looped biasing' with kelvin probe structure and canceling method for leakage contamination due to array peripherals. This test structure is implemented in scribe line for 28nm technology and beyond. And we get layout dependency of MOSFET characteristics and mismatch characteristics.
[Show abstract][Hide abstract] ABSTRACT: In this work CPI induced mechanical stress for 3D stacks and 3D interposer packages is studied. The stress built during package assembly has been obtained using finite element modeling (FEM). For the package layout and materials properties chosen for this work, the results shown that the stresses induced during the processing of a 3D stacks and 3D interposer configuration are similar when they are assembled in a Flip Chip Ball Grid Array (fcBGA) package. Furthermore, the interconnection between the different silicon dies assured with the use of μbumps were analyzed with different interconnect densities and configurations. Results shown that stress induced around the μbumps increases by increasing the μbump pitch. Different molding configurations for the fcBGA packages were investigated, including high power (exposed die) and low power (embedded dies) packages. The results showed that exposed die packages present lower out of plane deformation due to a reduction of the epoxy mold compound (EMC) thickness. It is very important to accurately calculate the residual stresses that each processing steps of the assembly induced on the die. Mass reflow and thermo compression bonding process assembly have been investigated. Results showed that solder joint reflow is the bottleneck for mass reflow process assembly, high stress in this step indicate that failures can occur. In this work we showed that low CTE laminate is a good alternative to reduce until 60% stress at flip chip reflow step.
[Show abstract][Hide abstract] ABSTRACT: Chip-package interaction (CPI) is becoming a critical issue for the reliability of back-end-of-line (BEOL) during or after package assembly. Complex BEOL layer stacks must have sufficient mechanical strength to survive the thermally induced stresses during processing or working lifetime. Therefore, it is necessary to assess possible failure mechanisms already at early phases of development so that the integrity of the chips can be guaranteed. This paper presents an advanced experimental stability test that combines a BABSI test (Bump Assisted BEOL Stability Indentation test) with in-situ monitoring of the induced stress during this test. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the bump (a Cu pillar) and finite element simulations.
[Show abstract][Hide abstract] ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.
[Show abstract][Hide abstract] ABSTRACT: Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack.
IEEE Transactions on Components, Packaging, and Manufacturing Technology 06/2014; 4(6):1026-1037. DOI:10.1109/TCPMT.2014.2316150 · 1.18 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A test system for memory-logic communications in silicon interposer is introduced as well as a performance analysis methodology including a fitted model based on eye diagram measurements. First results of the test system with 9 and 18 mm-long interconnects and a 5 channel bus of micro-strip lines with 2-2 and 5-5 μm width and spacing (W-S), targeting Wide-IO communication standard are presented. Measured eye diagrams allow us to compare the performance of the different test systems in combination with a fitted model. All considered systems show operation frequencies higher than 200 MHz for an eye height of at least 35 %. It is demonstrated that the communication system performance is mainly dominated due to weak driver strength (RS > 250 Ω) and secondly by the interconnection dimensions. Design considerations are proposed from the observed results.
2014 IEEE 18th Workshop on Signal and Power Integrity (SPI); 05/2014
[Show abstract][Hide abstract] ABSTRACT: This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.
2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
[Show abstract][Hide abstract] ABSTRACT: This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand the trade-offs due to the new devices and the upcoming process solutions to address them. Process features, variability and parasitics relevant to 14nm and beyond FinFET will be reviewed and their System-On-Chip (SOC) implications will be discussed.
2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
[Show abstract][Hide abstract] ABSTRACT: The ever increasing stress engineering raises a major concern of strong layout-dependent effects (LDE) in the advanced technology nodes. We report on the dependency of SiGe S/D and STI induced stress on fin length, position of the gate along the fin and fin to fin distances. The efficiency of epitaxial S/D SiGe stressors is reduced when the fin length is decreased and strongly degraded for fins with a single gate regardless of the SiGe depth, resulting in up to 21% performance degradation at ring oscillator level. Although tensile STI improves the NFETs mobility, the use of compressive STI guarantees a constant mobility ratio and limits the performance variation with layout.
[Show abstract][Hide abstract] ABSTRACT: Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400 °C range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. TSV aspect ratios can vary as function of the integration scheme, for instance in a via-last or via-middle flow, and thus barrier continuity requires conformality which guarantees the presence of a diffusion barrier until the bottom of the TSV. Target conformality can either be obtained by PVD, typically for TSV A.R. ⩽ 10:1. We report on the thermal stability of Ta, and Ti barriers and we show that 5 nm PVD Ta barriers are thermally stable, while PVD Ti-barriers require thicknesses above 5 nm to guarantee their thermal stability.