G. Van der Plas

imec Belgium, Louvain, Flanders, Belgium

Are you G. Van der Plas?

Claim your profile

Publications (137)66.74 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.
    Microelectronics Reliability 06/2014; · 1.14 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A test system for memory-logic communications in silicon interposer is introduced as well as a performance analysis methodology including a fitted model based on eye diagram measurements. First results of the test system with 9 and 18 mm-long interconnects and a 5 channel bus of micro-strip lines with 2-2 and 5-5 μm width and spacing (W-S), targeting Wide-IO communication standard are presented. Measured eye diagrams allow us to compare the performance of the different test systems in combination with a fitted model. All considered systems show operation frequencies higher than 200 MHz for an eye height of at least 35 %. It is demonstrated that the communication system performance is mainly dominated due to weak driver strength (RS > 250 Ω) and secondly by the interconnection dimensions. Design considerations are proposed from the observed results.
    2014 IEEE 18th Workshop on Signal and Power Integrity (SPI); 05/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack.
    IEEE Transactions on Components, Packaging, and Manufacturing Technology 01/2014; 4(6):1026-1037. · 1.26 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.
    2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand the trade-offs due to the new devices and the upcoming process solutions to address them. Process features, variability and parasitics relevant to 14nm and beyond FinFET will be reviewed and their System-On-Chip (SOC) implications will be discussed.
    2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The ever increasing stress engineering raises a major concern of strong layout-dependent effects (LDE) in the advanced technology nodes. We report on the dependency of SiGe S/D and STI induced stress on fin length, position of the gate along the fin and fin to fin distances. The efficiency of epitaxial S/D SiGe stressors is reduced when the fin length is decreased and strongly degraded for fins with a single gate regardless of the SiGe depth, resulting in up to 21% performance degradation at ring oscillator level. Although tensile STI improves the NFETs mobility, the use of compressive STI guarantees a constant mobility ratio and limits the performance variation with layout.
    VLSI Circuits (VLSIC), 2013 Symposium on; 06/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Through 3D-IC Integration is possible to put more transistors on the same footprint without the need to shrink transistor sizes. As for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing. In this work we introduce the several processes to generate 3D stacked devices. We focus on processes like TSV, wafer thinning, backside passivation, back side RDL (Re-Distribution Layer), front side and backside μbumping. We report on the characterization of the effects on transistor devices due to TSV proximity, wafer thinning and die stacking. The transistor devices are based on imec CMOS technology and are manufactured on 300mm diameter wafers. The wafers are fully processed with Front End of Line (FEOL), Back End Of Line (BEOL), wafer thinning on Si carrier, back-side wafer bumping, carrier de-bonding, dicing and final 3D-stacking. We report the main electrical characterizations done to identify the impact of typical 3D processes on CMOS devices. The characterizations are performed in-line (clean room compatible test equipment) and confirmed offline (standard testing equipment out of clean room environment). To characterize the process steps of interest, we use dedicated test structures that are measured before and after the process. The dedicated test structures are mainly measured after wafer front side processing (FEOL and BEOL) and tested again after wafer thinning and after die stacking. The measured variations (typically ION currents) are later elaborated to illustrate the process effect. In case of 3D stacks, the characterization is executed for two-dies stacking. To have an assessment of the 3D stacking yield, the dies are connected by TSVs-μbumps in several daisy chain configurations.
    Microelectronics Packaging Conference (EMPC) , 2013 European; 01/2013
  • X. Sun, J. Ryckaert, G. Van der Plas, E. Beyne
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper investigates the RF properties of 5 μm diameter/50 μm depth through-silicon vias (TSVs) built in CMOS 65nm technology. An equivalent lump model of the TSVs was developed based on 3D full-wave electromagnetic simulations and was validated by RF measurements. Based on the validated TSV model, the crosstalk among the TSVs was addressed as a function of distance and frequency. An equivalent lump model of the TSV-to-TSV crosstalk was also developed. Good agreement was obtained between simulations and measurements. Additionally, the noise peak vs. TSV-to-TSV distance and the crosstalk noise as a function of rise time was also investigated. It was found that the crosstalk noise decreased and the noise width increased with increasing signal rise time. A short signal rise time should thus be applied only if high speed is really required.
    Microelectronics Packaging Conference (EMPC) , 2013 European; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, the thermal performance and the thermal die-to-die coupling are compared for the case of a 3D stacked configuration and a Si TSV-interposer by means of detailed thermal finite element simulations. The comparison is applied to packages with two components: 10×10mm2 logic chip and a 2×10mm2 temperature sensitive SerDes chip. A one-to-one comparison is made for package configurations without heat sink and for packages with integrated heat spreader and high performance heat sink.
    Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Efficient processing of fine-pitched Through Silicon Vias, micro-bumps and back-side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows typically conceived for 2D systems. With all system, technology and implementation level options brought with these features, the design space increases to an extent where traditional 2D tools cannot be used any more for efficient exploration. Therefore, the cost-effective design of future 3D ICs products will require new planning and co-optimisation techniques and tools that are fast and accurate enough to cope with these challenges. In this paper we present design methodology and the practical EDA tool chain that covers different aspects of the design flow and is specific to efficient design of 3D-ICs. Flow features include: fast synthesis and 3D design partitioning at gate level, TSV/micro-bump array planning, 3D floor planning, placement and routing, congestion analysis, fast thermal and mechanical modeling, easy technology vs. implementation trade-off analysis, 3D device models generations and Design-for-Test (DfT). The application of the tool chain is illustrated using concrete example of a real-world design, showing not only the applicability of the tool chain, but also the benefits of heterogeneous 2.5 and 3D integration technologies.
    Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: We propose a test structure named difference charge-based capacitance measurement (DCBCM) for measuring matching of MOM capacitance with better than 10 atto-farad (aF) accuracy and MOS capacitance with few tens of aF accuracy. The test structure is a derivative of the Charge-based Capacitance measurement (CBCM) technique [1]. In the structure two matched (or intentionally mismatched) capacitors are charged with alternating voltages on one side and on the other side the charges are alternated between two output nodes. We can eliminate parasitic leakage and charge injection components and extract the capacitance difference from the resulting output current that is proportional to the capacitance difference. It is found that mismatch of 20fF MOM capacitances with intentionally 100aF offset can be measured with 7.2aF absolute accuracy. With an adequate input pulse scheme, we also demonstrated a measurement of 100-200fF MOS capacitance mismatch with bias voltage dependence which showed sensitivity of σ = 0.06%. The proposed DCBCM technique is suitable for evaluating small capacitance mismatch for beyond 20nm node.
    Microelectronic Test Structures (ICMTS), 2013 IEEE International Conference on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Due to their large volume and close proximity to devices, the reliability of copper TSV's is a concern, both with respect to mechanical stresses induced by the TSV in the Si and with respect to copper drift into the liner and the Si. This abstract summarizes recent achievements obtained in imec's 3D-reliability work package where above mentioned reliability concerns are evaluated in detail. To study the impact of mechanical stresses induced by the TSV in the Si, the saturation drain currents Id of transistors have been used as stress sensors. The offset of the Id of transistors closer to a TSV with respect to transistors far away from a TSV has been studied, both directly after processing and after thermal storage and thermal shock. It is shown that stresses generated by the TSV in the Si increase after thermal storage above certain temperatures while thermal shock reduces these stresses. The first is attributed to stress relaxation at high temperatures, while the latter is attributed to cracking/delamination at critical interfaces. To study continuity in TSV-barriers, a method, further referred to as dual ramp rate IVctrl, is introduced. The method consists of controlled current-voltage sweeps at different rates. The difference in breakdown fields for different ramp rates allows estimating TDDB (=Time Dependent Dielectric Breakdown) field acceleration parameters. Applying a negative voltage to the TSV (-V) does not allow copper to drift into the liner, while when applying a positive voltage (+V) to the TSV, copper can drift into the liner in case of a defective, non-continuous barrier. Comparing TDDB field acceleration parameters of -V versus +V tests gives insight in barrier properties. In our study, weak reliability is observed in systems where the TSV-barriers are not continuous.
    Physical and Failure Analysis of Integrated Circuits (IPFA); 07/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: FET arrays are investigated from the viewpoint of Chip-Package Interaction (CPI) sensor suitability and presented as a possible solution for experimental characterization of CPI effects during 3D assembly steps: Stacking and packaging. The study presents a methodology consisting of an experimental approach with the support of FEM modeling. The use of the transistors as stress sensors covering in-plane stress components is justified, after which the applicability of the transistors to the actual stacking and packaging stress states is discussed. Calibration to in-plane stress of long and short channel transistors, p and n type, is performed to obtain sensor sensitivities and link stress to current shift by according calculated piezocoefficients. Testing the FET arrays as sensors is firstly done by means of a simple structure where a die is glued to a plastic substrate. The electrical measurements are compared to FEM models and profilometric scans. The sensors are next utilized to obtain first results from 3D stacking and packaging. The underfill - microbump mechanism in a 2-die stack is quantified and initial results on overmould impact are discussed.
    International Reliability Physics conference; 04/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: Besides the stress around Cu TSV's, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.
    01/2012;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The 3D IC stacking technology with Through Silicon via (TSV) approach promises lower cost, smaller footprint and higher performance for heterogeneous system integration. D integration technology needs key components to be enabled: Like TSV technology, Wafer thinning, thin wafer carrier and handling technology and μbumps interconnects. In the via-middle 3D-Stacked IC approach, Cu filled TSVs are integrated after device fabrication and before metal 1. The stress patterns around TSV's and μbumps are considered as important concerns for 3D integration, as this leads to additional variability in MOSFET mobility, threshold voltage, and drivability. This contribution reviews the assessment of TSV and μbumps proximity effects on FEOL device performance.
    01/2012;
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration.
    Electron Devices Meeting (IEDM), 2012 IEEE International; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: 3D-TSV technologies promise increased system integration at lower cost and reduced footprint. One of the most likely applications of 3D technology is the integration DRAM-on-logic. Thermal management issues are considered one of the potentially showstoppers for 3D-integration. In this paper, we present a thermal experimental and modeling characterization of a packaged DRAM on logic stack. The DRAM die is stacked to the thinned logic die (25μm) using CuSn microbumps. For the experimental characterization a dedicated logic chip with integrated heaters and sensors is used. The thermal impact of logic hot spot dissipation on the temperature profile of the DRAM and the logic die is experimentally characterized in a dedicated socket using two experimental configurations mimicking a high power and a low power configuration respectively. The use of those 2 different experimental configurations of the packaged stack allows the calibration of a detailed finite element thermal model. The calibrated thermal models are used to evaluate the impact of the effective thermal conductivity of the microbump and underfill layer and the impact of the logic die thickness on the temperature distribution in the logic and DRAM die for different cooling configurations of the die stack.
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: The effect of thermal cycling, accelerated thermal storage and long-term storage at room temperature on the performance of FEOL devices integrated together with through silicon vias (TSVs) is studied. The transistor performance is used as monitor of stress induced in the Si by the TSV. It is observed that storage at high temperatures increases the stress in the Si induced by the TSV while thermal cycling and long- term storage at room temperature decreases this stress. These stress variations are hypothesized to be due to creep of copper in the TSV.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: Power and substrate domains are strategically isolated or unified in heterogeneous 3D integration. In-tier probing circuitry provides accessibility to power delivery and substrate networks in a deep tier of a 3D chip stack and capability of diagnosing intra/inter tier coupling. A two-tier demonstrator was successfully tested in a 130 nm CMOS, 3D-SIC Cu TSV technology.
    3D Systems Integration Conference (3DIC), 2011 IEEE International; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal-mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.
    IEEE Transactions on Semiconductor Manufacturing 01/2012; 25(3):365-371. · 0.86 Impact Factor

Publication Stats

1k Citations
66.74 Total Impact Points

Institutions

  • 2003–2014
    • imec Belgium
      • Smart Systems and Energy Technology
      Louvain, Flanders, Belgium
  • 1994–2009
    • University of Leuven
      • Department of Electrical Engineering (ESAT)
      Louvain, Flanders, Belgium
  • 2007
    • Free University of Brussels
      • Electricity (ELEC)
      Bruxelles, Brussels Capital Region, Belgium
  • 2006
    • Università di Pisa
      • Department of Information Engineering
      Pisa, Tuscany, Italy