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ABSTRACT: A digital signal processor (DSP) system-on-chip (SoC) can be designed using a variety of architectures and techniques. This often presents different verification challenges compared to conventional SoC or processor designs. Verification of such designs should take into account the goals and applications of the DSP, and how they are eventually used. This paper proposes an application based verification methodology and demonstrates this technique on a real-life DSP SoC design. Our technique employs a library of specially devised application functions as test building blocks, followed by a genetic evolutionary test generator to compose these application functions into effective test programs.
Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on; 02/2008
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ABSTRACT: Very long instruction word (VLIW) processors are generally implemented as clustered architectures in order to reduce delay, area and power when function units increase. However, a side effect of clustered architectures is processor performance degradation, due to additional latency and copy operations from data transfers between these clusters. Therefore, appropriate scheduling algorithms must be applied to overcome this. This paper presents a new register-file-connectivity clustered VLIW (RFCC-VLIW) architecture, in which a global register file is used to transfer data between clusters. Using the global register file, latency and copy operations can be eliminated. Additionally, the paper presents a scheduling algorithm for the RFCC-VLIW architecture. The two-dimension force-directed algorithm can assign instructions evenly to all clusters and reduce usage of ports and global registers. Experimental results show our algorithm outperforms other scheduling algorithms for clustered VLIW when targeted toward RFCC-VLIW architectures.
Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on; 08/2007
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ABSTRACT: This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian; 12/2006
