Zhikuan Zhang

The Hong Kong University of Science and Technology, Kowloon, Hong Kong

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Publications (13)11.18 Total impact

  • Wen Wu, Zhikuan Zhang, Mansun Chan
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    ABSTRACT: This paper studies the minimization of parasitics in multi-fin MOS devices. A distributed RC model is provided to minimize the gate resistances and the influence of device geometrical parameters on gate RC delay is thoroughly investigated. Also, we give a criterion to achieve the minimal gate resistance for RF device design. Furthermore, methods of reducing source/drain parasitic resistances and capacitances are discussed.
    Electron Devices and Solid-State Circuits, 2005 IEEE Conference on; 01/2006
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    ABSTRACT: In this paper, we had proposed a silicon integrated circuit (IC) compatible DNA-detection platform using photodiode and ordinary optical illumination to detect DNA hybridization events occurred on the chip surface. The method utilizes gold nanoparticle labeling and silver enhancement to generate opaque surface at area with target DNA hybridization. A photodiode fabricated underneath the supporting surface can then be used to detect the light intensity changes, before and after the silver enhancement. With this technique, we have successfully discriminated single base-mismatched DNA from matched DNA sequence, and the detection limit could be as low as 10 pM. By exploiting the advanced modern IC manufacturing technology and the well-established electrochemical immobilization of DNA, this approach has the potential to be used to construct a portable high-density DNA nanoarray system with fully electronic readout.
    Sensors and Actuators B: Chemical. 01/2005;
  • Zhikuan Zhang, Shengdong Zhang, Mansun Chan
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    ABSTRACT: In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.
    IEEE Electron Device Letters 12/2004; · 2.79 Impact Factor
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    ABSTRACT: We propose a silicon integrated circuit (IC) compatible DNA detection platform based on the interaction of self-assembled nano-metallic particles and ordinary visible light. The DNA hybridization initiates the formation of an opaque area at the surface of the support. A photodiode array fabricated underneath the supporting surface can then be used to detect the light intensity changes before and after the assembly of the nano-particle; the signal can be further amplified by silver enhancement.
    Sensors, 2004. Proceedings of IEEE; 11/2004
  • Zhikuan Zhang, Shengdong Zhang, Mansun Chan
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    ABSTRACT: In this work, a self-aligned recessed source/drain (ReS/D) ultra-thin body (UTB) SOI MOS technology is proposed and demonstrated. The thick diffusion regions of the ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic source/drain resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated source/drain structure. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated. Fabrication details and experimental results are presented.
    Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European; 10/2004
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    ABSTRACT: The advantages of using elevated S/D formed on oxide shallow trench isolation are studied in detail. By careful design, the short channel short channel effects can be suppressed by the elevated source/drain (S/D) structure. In addition, the S/D region parasitic capacitance is significantly suppressed by the silicon-on-insulator (SOI)-like S/D structure. Tradeoff between series resistance and gate-to-drain Miller capacitance can be achieved by carefully selecting the gate spacer thickness. With careful optimization of device geometry, both the gate-delay and power consumption can be significantly reduced together. Design guideline and potential performance gain with the S/D-on-insulator structure is discussed.
    IEEE Transactions on Electron Devices 08/2004; · 2.06 Impact Factor
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    ABSTRACT: As MOSFET feature sizes are scaled to the deep sub-0.1 μm regime, ultra-shallow source/drain extensions and heavily doped halos are required to suppress short-channel effects. These structures result in high series resistance and parasitic capacitance. A source/drain-on-insulator (SDOI) structure with elevated source/drain combined with an oxide isolation, formed by a shallow trench process underneath the source/drain region, is reported to be a potential solution to simultaneously reduce the series resistance and parasitic capacitance. However, the optimization of SDOI structures is very tricky and the tradeoff between series resistance and gate-to-drain Miller capacitance is not obvious. In this paper, the advantage of this MOSFET source/drain engineered structure is verified by detailed device simulation with extremely scaled MOSFETs. Device structure parameter optimizations are discussed to maximize the intrinsic performance. Design guidelines and potential performance gain with the SDOI structure are also discussed.
    Device Research Conference, 2004. 62nd DRC. Conference Digest [Includes 'Late News Papers' volume]; 07/2004
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    ABSTRACT: A high-density CMOS-compatible deoxyribonucleic acid (DNA) array fabricated with a modified metallization process is demonstrated. The array consists of silicon nitride isolation to confine the DNA sample to a specific cell area defined by silicon dioxide to achieve low crosstalk between neighboring cells. A prehybridization process together with a conductive enhancement method are also developed to improve the signal to noise ratio. Nine orders of magnitude difference in conductance is measured between array cells with matched and single-based mismatched DNA samples. The matching of DNA molecules can then be easily detected by a simple digital switching circuit.
    IEEE Transactions on Electron Devices 11/2003; · 2.06 Impact Factor
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    ABSTRACT: A high-density CMOS-compatible DNA array fabricated using a modified metalization process is demonstrated. The array produces a conductivity difference of nine orders of magnitude for matched and single-based mismatched DNA molecules, which can be easily detected by a simple sensing circuit.
    Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International; 02/2003
  • Source
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    ABSTRACT: In this paper, a source/drain structure separated from the silicon substrate by oxide isolation is fabricated and studied. The source/drain diffusion regions are connected to the shallow source/drain extension through a smaller opening defined by a double spacer process. Experimental results indicate that the source/drain on insulator significantly reduces the parasitic capacitance. Further optimization by simulation indicates a reduction of series resistance and band-to-band drain leakage at off-state can be achieved in extremely scaled devices. Compared with the conventional planner source/drain structure, the reduction of parasitic capacitance and series resistance can be as much as 80% and 30% respectively.
    Solid-State Electronics 01/2003; 47(10):1829-1833. · 1.48 Impact Factor
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    ABSTRACT: This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.
    IEEE Electron Device Letters 11/2002; · 2.79 Impact Factor
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    ABSTRACT: The effects of grain boundaries on the performance of super TFTs formed by MILC are studied. The existence of grain boundaries in the channel region will cause subthreshold hump, early punchthrough or device degradation, depending on the direction of the grain boundaries. The probability for the channel region of a TFT to cover multiple grains decrease significantly when the device is scaled down, thus resulting in better device performance and higher uniformity. A novel method to measure the grain dimension by using boundaries oxide as a etching mask has also been developed
    Electron Devices Meeting, 2000. Proceedings. 2000 IEEE Hong Kong; 02/2000
  • Source
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    ABSTRACT: The scaling properties of the large-grain polysilicon on insulator (LPSOI) MOSFETs are investigated. In conventional small grain polysilicon TFT, the defect related field emission at the drain end is the main source of device failure. With the device width scaling of LPSOI MOSFETs such effects reduces significantly. Therefore, a deeper scaling of the channel length of narrow LPSOI MOSFETs is possible, and lead to a significantly improved device performance. However, the short channel effects like DIBL start appearing after a certain channel length. A study of these effects can be used to optimize device and process design for high performance on MOSFETs on the LPSOI substrate.

Publication Stats

46 Citations
11.18 Total Impact Points

Institutions

  • 2000–2006
    • The Hong Kong University of Science and Technology
      • Department of Electronic and Computer Engineering
      Kowloon, Hong Kong
  • 2005
    • Southeast University (China)
      Nan-ching-hsü, Jiangxi Sheng, China