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ABSTRACT: A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.
Journal of Semiconductors 08/2009; 30(8):085010.
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ABSTRACT: A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5 ¿m CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5 mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900 e. The power dissipation without the output buffer is about 2.6 mW.
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
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ABSTRACT: This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL. The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly. The maximum calibration time is less than five comparison periods. With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole working range. The proposed circuit has been implemented in 0.18 um CMOS logic process. Results show that the calibration time is less than 1.2¿s, and the total locking time is less than 3¿s. The PLL has good jitter performance within its operating range from 860 MHz to 2.1GHz.
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
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ABSTRACT: A novel data-sparsification method for multi-channel radiation detector readout ASICs is proposed. Based on the self-triggering approach, the scheme operates as follows: when one channel is being read out, the trigger signal from other channels is delayed one or more clock cycles and then processed. In this way, the dead time, during which the circuit fails to respond to the input, is reduced and so is the error rate. A 16-channel readout ASIC has been designed in a 0.5um DPTM CMOS technology. The feasibility of this novel sparse readout method is verified by simulation. Theory analysis and calculation show that the error rate is approximately 2.5%, and is reduced by about 37% compared with the conventional scanning scheme, assuming a 16-channel system with an event rate of 100 K/s per channel.
ASIC, 2007. ASICON '07. 7th International Conference on; 11/2007
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ABSTRACT: This paper presents a low jitter adaptive-bandwidth charge pump PLL with an improved passive filter. With an adaptive bandwidth, the proposed PLL maintains optimal performance over its whole operating range. In order to improve the jitter performance of the PLL, matching technique is employed in the charge pump, and a voltage-to-voltage converter is used to achieve a low gain VCO. The novel circuit has been implemented in 0.35 mum CMOS process. Post simulation results show that the PLL can scale its loop dynamics proportional to the operating frequency and has good jitter performance within its operating range from 100 MHz to 1.1 GHz.
ASIC, 2007. ASICON '07. 7th International Conference on; 11/2007
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ABSTRACT: A 10-bit 80 MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5 um technology, the ADC dissipates 210 mw of power from a 5 v supply, and achieves a peak SNDR of 56 dB at 80 Ms/s.
ASIC, 2007. ASICON '07. 7th International Conference on; 11/2007
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ABSTRACT: A precise curvature compensated CMOS bandgap voltage reference is presented, which utilizes temperature-independent current and an improved voltage-transfer unit to compensate for the higher order of the V<sub>BE</sub>. The new proposed bandgap voltage reference is implemented in 0.13 mum CMOS technology and operates with 0.9V supply voltage consuming 48muW at room temperature. The circuit achieves 5ppm/degC of temperature coefficient with temperature range from -40 to 85degC. With 0.9V supply voltage, the power noise rejection ratio is -25 dB at 10 kHz
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on; 02/2006
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ABSTRACT: A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm<sup>2</sup>has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on; 01/2006
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ABSTRACT: This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on; 01/2006
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ABSTRACT: A novel method to adjust gain in CMOS infrared (IR) readout integrated circuit (ROIC) which is suitable for the application of small pixel size has been proposed in this paper. Current mirror is inserted in the pixel to adjust gain. Two comparators have been added outside of the pixel and provide the decision to select different gains. Adjustable gain makes the design of following signal process circuit easier and allows long integration time to increase SNR. With this method of automatic gain adjust, ROIC can deal with the current that varies from 40nA to 300nA, with the integration capacitor of 2pF and the integration time of 40μs. An experimental 4×4-pixel ROIC has been designed and it will be fabricated with 0.5μm DPDM n-well CMOS process.
ASIC, 2005. ASICON 2005. 6th International Conference On; 11/2005
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ABSTRACT: A 12-bit 20MS/s low power pipelined analog-digital converter (ADC) is presented. A front-end sampling network is proposed to eliminate the need of SHA. Passive capacitor error-averaging technique (PCEA) and Opamp sharing scheme are employed to achieve high resolutions and low power and area. The drawback of conventional Opamp sharing technique is resolved with polarity inverting scheme by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um mix-signal CMOS technology, the ADC dissipates 71mw from a 5V supply, and achieves a peak SNDR of 69.8dB with a 0.5MHz full-scale sine input at 20MS/s.
Signal Processing Systems, International Conference on.
