-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt , the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/ f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/ f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/ f model developed is discussed.
IEEE Transactions on Nanotechnology 06/2011; · 2.29 Impact Factor
-
Rock-Hyun Baek,
Chang-Ki Baek,
Sang-Hyun Lee,
Sung Dae Suk,
Ming Li, Yun Young Yeoh,
Kyoung Hwan Yeo,
Dong-Won Kim,
Jeong-Soo Lee,
D.M. Kim,
Yoon-Ha Jeong
[show abstract]
[hide abstract]
ABSTRACT: Presented in this letter are the C - V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C - V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated using C - V data, and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance R <sub>sd</sub>. These observed data are compared with the data from planar MOS capacitor.
IEEE Electron Device Letters 03/2011; · 2.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The series resistance, R <sub>sd</sub> in silicon nanowire FETs (Si-NWFET) is extracted unambiguously, using the Y -function technique, in conjunction with the drain current and transconductance data. The volume channel inversion in Si-NWFET renders the charge carriers relatively free of the surface scattering and concomitant degradation of mobility. As a result, the Y -function of Si-NWFET is shown to exhibit a linear behavior in strong inversion, thereby enabling accurate extraction of R <sub>sd</sub>. The technique is applied to nanowire devices with channel lengths 82, 86, 96, 106, 132, and 164 nm, respectively. The extracted R <sub>sd</sub> values are shown nearly flat with respect to the gate voltage, as expected from Ohmic contacts but showed a large variation for all channel lengths examined. This indicates the process parameters involved in the formation of series contacts vary considerably from device to device. The present method only requires a single device for extraction of R <sub>sd</sub> and the iteration procedure for data fitting is fast and stable.
IEEE Transactions on Nanotechnology 04/2010; · 2.29 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, sub-10 nm gate-all-around (GAA) CMOS silicon nanowire field-effect transistors (SNWFET) on bulk Si substrate are fabricated successfully for the first time with 13-nm-diameter silicon nanowire channel. On-state currents of 1494/1054 muA/mum at off leakage currents of 102/6.44 nA/mum are obtained for N/PMOS, respectively. The impacts of nanowire diameter (D<sub>NW</sub>) and gate oxide thickness (T<sub>OX</sub>) as well S/D parasitic resistance (R<sub>SD</sub>) on performance are investigated in details.
VLSI Technology, 2009 Symposium on; 07/2009
-
Sung Dae Suk,
Ming Li, Yun Young Yeoh,
Kyoung Hwan Yeo,
Jae Kyu Ha,
Hyunseok Lim,
HyunWoo Park,
Dong-Won Kim,
TaeYoung Chung,
Kyung Seok Oh,
Won-Seong Lee
[show abstract]
[hide abstract]
ABSTRACT: Sub 5 nm tri-gate nanowire MOSFET is successfully developed with good uniformity by using conventional technology in the SOI structure. Performance of the poly Si channel is compared with that of the single Si channel. On-state current of n-FET has attained to 802 uA/um for single Si channel, while 471 uA/um for poly Si channel, which is 60 % of performance of the single Si channel at L<sub>G</sub> ~ 5 nm due to the enhancement of ballistic efficiency. At the extremely small L<sub>G</sub> of around 5 nm, we also investigate off-leakage current with boosted BJT operation.
VLSI Technology, 2009 Symposium on; 07/2009
-
[show abstract]
[hide abstract]
ABSTRACT: Hot carrier (HC) reliability of gate-all-around twin Si nanowire field effect transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2 nm thickness show worse hot carrier reliability. The worst V<sub>D</sub> for 10 years guaranty, 1.31 V, satisfies requirement of ITRS roadmap.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
-
[show abstract]
[hide abstract]
ABSTRACT: In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at off current of 1nA/mum for NMOS and PMOS, respectively.
SOI Conference, 2008. SOI. IEEE International; 11/2008
-
Kyoung Hwan Yeo,
Keun Hwi Cho,
Ming Li,
Sung Dae Suk, Yun-young Yeoh,
Min-Sang Kim,
Hyunjun Bae,
Ji-Myoung Lee,
Suk-Kang Sung,
Jun Seo,
Bokkyoung Park,
Dong-Won Kim,
Donggun Park,
Won-Seoung Lee
[show abstract]
[hide abstract]
ABSTRACT: Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, V<sub>TH</sub> window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire width is, the faster program speed and the larger V<sub>TH</sub> shift are achieved. P/E operations in NAND string with GAA SONOS nanowire are demonstrated for the first time.
VLSI Technology, 2008 Symposium on; 07/2008
-
[show abstract]
[hide abstract]
ABSTRACT: I<sub>ON</sub> is increased about 25 % with the width/height (W/H) of 12/24 nm nanowire (NW) in comparison with the W/H of 12/12 nm at V<sub>G</sub>-V<sub>TH</sub> = 1 V. With these results, we have successfully fabricated NW SRAM arrays with the W/H of 5/15 nm and LG of 40 nm for the first time. Static noise margin (SNM) of 325 mV is achieved at V<sub>D</sub> = 1 V. NW height and gate oxide thickness dependency of n-ch twin silicon nanowire MOSFET (TSNWFET) on device variations is investigated. Line edge roughness and size variation are more critical than random dopant fluctuation in TSNWFET.
VLSI Technology, 2008 Symposium on; 07/2008
-
Sung Dae Suk,
Kyoung Hwan Yeo,
Keun Hwi Cho,
Ming Li, Yun Young Yeoh,
Sung-Young Lee,
Sung Min Kim,
Eun Jung Yoon,
Min Sang Kim,
Chang Woo Oh,
Sung Hwan Kim,
Dong-Won Kim,
Donggun Park
[show abstract]
[hide abstract]
ABSTRACT: A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.
IEEE Transactions on Nanotechnology 04/2008; · 2.29 Impact Factor
-
Sung Dae Suk,
Ming Li, Yun Young Yeoh,
Kyoung Hwan Yeo,
Keun Hwi Cho,
In Kyung Ku,
Hong Cho,
WonJun Jang,
Dong-Won Kim,
Donggun Park,
Won-Seong Lee
[show abstract]
[hide abstract]
ABSTRACT: Nanowire size (dNW) dependency of various electrical characteristics on gate all around twin silicon nanowire MOSFET (TSNWFET) is investigated to understand overall performance of nanowire transistor deeply. When dNW decreases, current drivability (Ion) normalized by circumference at the same VG-VTH improves and maximizes at dNW of 4 nm. And mobility is also estimated with capacitance and series resistance. All the experimental investigation shows that dNW of 4 nm is the best point to maximize the volume inversion effect on gate all around nanowire MOSFET.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
-
[show abstract]
[hide abstract]
ABSTRACT: Strained silicon nanowire transistor with embedded SiGe (e-SG) source/drain is investigated for the first time on experiments. By compressive stress induced by e-SG, PMOS performance is improved by about 85%. <110>-oriented nanowire channel also contributes 80% PMOS performance improvement relative to <100> direction. By combination of uniaxial stress and <110> channel direction, up to 136% PMOS performance enhancement is obtained so that superior PMOSFET to NMOSFET is for the first time observed with silicon channel material.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
-
Keun Hwi Cho,
Sung Dae Suk, Yun Young Yeoh,
Ming Li,
Kyoung Hwan Yeo,
Dong-Won Kim,
Donggun Park,
Won-Seong Lee,
Young Chai Jung,
Byung Hak Hong,
Sung Woo Hwang
[show abstract]
[hide abstract]
ABSTRACT: The characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with a radius of 5 nm have been measured in temperatures T ranging from 4 to 300 K. The dependence of the off-current suggests that thermal generation in the channel is the main leakage mechanism. The dependence of the subthreshold swing exhibits no body effects but shows degradations due to slight differences in the threshold voltages and in the body effect constants of the twin nanowires. The T dependence of the peak normalized transconductance g<sub>m</sub> /V<sub>DS</sub> gives a clue of 1-D phonon scattering and suggests that surface roughness scattering at the nanowire wall is dominant at low values.
IEEE Electron Device Letters 01/2008; · 2.85 Impact Factor
-
Sung Dae Suk,
Kyoung Hwan Yeo,
Keun Hwi Cho,
Ming Li, Yun young Yeoh,
Ki-Ha Hong,
Sung-Han Kim,
Young-Ho Koh,
Sunggon Jung,
WonJun Jang,
Dong-Won Kim,
Donggun Park,
Byung-II Ryu
[show abstract]
[hide abstract]
ABSTRACT: We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mus at V<sub>d</sub> = 2 V, V<sub>g</sub> = 6 V and erase speed of 1 ms at V<sub>d</sub> = 4.5 V, V<sub>g</sub> = -6 V are achieved with 2~3 nm nanowire and 30 nm gate. Nanowire size below 10 nm dependencies on V<sub>th</sub> shift (DeltaV<sub>th</sub>) and the program/erase (P/E) characteristics are investigated. As nanowire diameter (d<sub>nw</sub>) decreases, faster program speed and larger DeltaV<sub>th</sub> are observed.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
-
Kyoung Hwan Yeo,
Sung Dae Suk,
Ming Li, Yun-young Yeoh,
Keun Hwi Cho,
Ki-Ha Hong,
SeongKyu Yun,
Mong Sup Lee,
Nammyun Cho,
Kwanheum Lee,
Duhyun Hwang,
Bokkyoung Park,
Dong-Won Kim,
Donggun Park,
Byung-Il Ryu
[show abstract]
[hide abstract]
ABSTRACT: GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/mum while n-TSNWFET shows on-current of 1.44 mA/mum. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3D and quantum simulation
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
-
[show abstract]
[hide abstract]
ABSTRACT: the authors report transport experiments on gate-all-around (GAA) TSNWFETs fabricated by top-down CMOS processes. The nanowire with 45 nm gate length exhibits single electron tunneling, and the total capacitance extracted from the measured data is in good agreement with the self-capacitance of an ideal cylinder. The nanowire with 125 nm gate length shows conductance quantization suggesting ballistic transport. The temperature dependence of the conductance steps is consistent with the crossover from classical to ballistic
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
-
[show abstract]
[hide abstract]
ABSTRACT: This paper describes TSNWFET devices with embedded Si<sub>1-x</sub>Ge<sub>x</sub> source/drain regions and different nanowire orientations. Thick Si<sub>1-x</sub>Ge<sub>x</sub> embedded source/drain and lang110rang channel orientation is found effective to enhance p-channel TSNWFET performance, while cause degradation for n-channel one. Thin Si<sub>1-x</sub>Ge<sub>x</sub> and lang100rang channel orientation is the preferred combination for keeping n-TSNWFET performance. With lang110rang channel orientation and thick Si<sub>1-x</sub>Ge<sub>x</sub> in source/drain, p-MOS current, for the first time, is even observed to exceed its n-type counterpart from the experiments
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on; 11/2006
-
Sung Min Kim,
Eun Jung Yoon,
Min Sang Kim,
Sung Dae Suk,
Ming Li,
Lian Jun,
Chang Woo Oh,
Kyoung Hwan Yeo,
Sung Hwan Kim,
Sung Young Lee, [......],
Hong-Bae Park,
Chul Sung Kim,
Hye-Min Kim,
Dong-Chan Kim,
Heung Sik Park,
Hyung Do Kim,
Young Mi Lee,
Dong-Won Kim,
Donggun Park,
Byung-Il Ryu
[show abstract]
[hide abstract]
ABSTRACT: For the first time, titanium-nitride (TiN) single metal gate and high-k hafnium-silicate (HfSiO<sub>x</sub>) gate dielectric have been successfully integrated in 55nm McFET SRAM cell. The use of HfSiO<sub>x </sub> gate dielectric, not only reduces gate leakage current but also improves I<sub>ON</sub>/I<sub>OFF</sub> ratio of PFET to 10<sup>8</sup>. Using local fin implantation (LFI) scheme, junction capacitance is reduced by 13% and junction breakdown voltage is increased by 1.4V
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
