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ABSTRACT: In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase memory cells are presented for achieving high program inhibition with lower program disturbance in sub-40 nm MLC NAND flash and beyond. Simple two-step dynamic Vpass control technique is used and over 40% program failure reduction after 30 k P/E cycling is achieved in the proposed scheme, compared to conventional method. A major pattern dependency of program disturbance in MLC NAND flash is also described in this paper. In order to achieve high immunity for the data pattern dependency in program disturbance, optimizing erase Vth and its distribution using ISPP-after-erase with a precise negative Vth sensing scheme are proposed. The proposed schemes are demonstrated using 42 nm MLC NAND flash test chip and about 2 times better Vpass window margin is obtained compared to conventional scheme.
IEEE Journal of Solid-State Circuits 11/2010; · 3.23 Impact Factor
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ABSTRACT: This paper compares design concepts of 63nm-8Gb and 90nm-4Gb multilevel cell (MLC) NAND flash memory. For 8Gb MLC NAND flash memory, locations of peripheral circuits and charge pumps are determined to optimize area and signal speed. Page buffer is simplified by reducing the number of transistors with minimal connections thereby resulting in smaller size. Performance is improved by using fast-read/write cycle and reduced signal paths. Furthermore, two-MAT-cell-array architecture is used for 2times read/write operations. Various techniques are used to suppress noisy effects such as common source line (CSL) noise and floating-gate-coupling noise
Asian Solid-State Circuits Conference, 2005; 12/2005
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Dae-Seok Byeon,
Sung-Soo Lee, Young-Ho Lim,
Jin-Sung Park,
Wook-Kee Han,
Pan-Suk Kwak,
Dong-Hwan Kim,
Dong-Hyuk Chae,
Seung-Hyun Moon,
Seung-Jae Lee,
Hyun-Chul Cho,
Jung-Woo Lee,
Moo-Sung Kim,
Joon-Sung Yang,
Young-Woo Park,
Duk-Won Bae,
Jung-Dal Choi,
Sung-Hoi Hur,
Kang-Deog Suh
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ABSTRACT: An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 μm<sup>2</sup> and 133 mm<sup>2</sup>, respectively. Performance improves to 4.4 MB/s by using the 2× program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput to 23 MB/s.
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005
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Seungjae Lee,
Young-Taek Lee,
Wook-Kee Han,
Dong-Hwan Kim,
Moo-Sung Kim,
Seung-Hyun Moon,
Hyun Chul Cho,
Jung-Woo Lee,
Dae-Seok Byeon, Young-Ho Lim,
Hyung-Suk Kim,
Sung-Hoi Hur,
Kang-Deog Suh
[show abstract]
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ABSTRACT: A 4 Gb NAND flash memory with 2 b/cell uses 90 nm CMOS to achieve simultaneous data load during program operation with 1.6 MB/s program throughput. Fuse or pad-bonding switches it to a 2 Gb 1 b/cell NAND flash memory. The row decoder located in the middle of the cell array reduces W/L rise time and coupling noise. A program-after-erase technique and lowered floating poly thickness minimize cell Vth distribution.
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
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J. Lee,
Sung-Soo Lee,
Oh-Suk Kwon,
Kyeong-Han Lee,
Dae-Seok Byeon,
In-Young Kim,
Kyoung-Hwa Lee, Young-Ho Lim,
Byung-Soon Choi,
Jong-Sik Lee,
Wang-Chul Shin,
Jeong-Hyuk Choi,
Kang-Deog Suh
[show abstract]
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ABSTRACT: A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm<sup>2</sup> die size and a 0.044-μm<sup>2</sup> effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V<sub>CC</sub> in order to avoid program disturbance issues.
IEEE Journal of Solid-State Circuits 12/2003; · 3.23 Impact Factor
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June Lee,
Sung-Soo Lee,
Oh-Suk Kwon,
Kyeong-Han Lee,
Kyong-Hwa Lee,
Dae-Seok Byeon,
In-Young Kim, Young-Ho Lim,
Byung-Soon Choi,
Jong-Sik Lee,
Wang-Chul Shin,
Jeong-Hyuk Choi,
Kang-Deog Suh
[show abstract]
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ABSTRACT: A 1.8 V 2 Gb NAND flash memory is fabricated in a 90 nm process resulting in a 141 mm<sup>2</sup> die and a 0.044 μm<sup>2</sup> effective cell. To achieve the high level of integration, critical layers are patterned with KF photolithography and phase-shift masks with proximity correction.
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International; 02/2003
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June Lee,
Heung-Soo Im,
Dae-Seok Byeon,
Kyeong-Han Lee,
Dong-Hyuk Chae,
Kyong-Hwa Lee,
Sang Won Hwang,
Sung-Soo Lee, Young-Ho Lim,
Jae-Duk Lee,
Jung-Dal Choi,
Young-Il Seo,
Jong-Sik Lee,
Kang-Deog Suh
[show abstract]
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ABSTRACT: A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-μm CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 μm<sup>2</sup> and 129.6 mm<sup>2</sup>, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V<sub>DD</sub> is obtained.
IEEE Journal of Solid-State Circuits 12/2002; · 3.23 Impact Factor
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June Lee,
Heung-Soo Im,
Dae-Seok Byeon,
Kyeong-Han Lee,
Dong-Hyuk Chae,
Kyong-Hwa Lee, Young-Ho Lim,
Jung-Dal Choi,
Young-Il Seo,
Jong-Sik Lee,
Kang-Deog Suh
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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J. Lee,
Heung-Soo Im,
Dae-Seok Byeon,
Kyeong-Han Lee,
Dong-Hyuk Chae,
Kyong-Hwa Lee, Young-Ho Lim,
Jung-Dal Choi,
Young-Il Seo,
Jong-Sik Lee,
Kang-Deog Suh
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ABSTRACT: A 1.8 V 1 Gb flash memory uses a 0.12 μm STI process
technology. A charge pump operates at <1.8 V. A center-placed row
decoder is digitized in one block pitch by applying a 32-cell NAND
structure. A page buffer, containing two latches, supports a
cache-program to improve program speed to 7 MB/s
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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Taehee Cho,
Yeong-Taek Lee,
Eun-Cheol Kim,
Jin-Wook Lee,
Sunmi Choi,
Seungjae Lee,
Dong-Hwan Kim,
Wook-Ghee Han, Young-Ho Lim,
Jae-Duk Lee,
Jung-Dal Choi,
Kang-Deog Suh
[show abstract]
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ABSTRACT: A 116.7-mm<sup>2</sup> NAND flash memory having two modes, 1-Gb
multilevel program cell (MLC) and high-performance 512-Mb single-level
program cell (SLC) modes, is fabricated with a 0.15-μm CMOS
technology. Utilizing simultaneous operation of four independent banks,
the device achieves 1.6 and 6.9 MB/s program throughputs for MLC and SLC
modes, respectively. The two-step bitline setup scheme suppresses the
peak current below 60 mA. The wordline ramping technique avoids program
disturbance. The SLC mode uses the 0.5-V incremental step pulse and
self-boosting program inhibit scheme to achieve high program
performance, and the MLC mode uses 0.15-V incremental step pulse and
local self-boosting program inhibit scheme to tightly control the cell
threshold voltage V<sub>th</sub> distributions. With the small wordline
and bitline pitches of 0.3-μm and 0.36-μm, respectively, the cell
V<sub>t</sub>h shift due to the floating gate coupling is about 0.2 V.
The read margins between adjacent two program states are optimized
resulting in the nonuniform cell V<sub>t</sub>h distribution for MLC
mode
IEEE Journal of Solid-State Circuits 12/2001; · 3.23 Impact Factor
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Taehee Cho,
Young-Taek Lee,
Euncheol Kim,
Jinwook Lee,
Sunmi Choi,
Seungjae Lee,
Dong-Hwan Kim,
Wook-Kee Han, Young-Ho Lim,
Jae-Duk Lee,
Jung-Dal Choi,
Kang-Deog Suh
[show abstract]
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ABSTRACT: A 1 Gb NAND flash memory with 2b per cell uses 0.15 μm CMOS and
achieves simultaneous operation of 4 independent banks with 1.6 GMB/s
program throughput. Fusing enables changing to 512 Mb 1b-per-cell NAND
flash memory. Wordline ramping minimizes noise and peak current. Disturb
mechanisms and noise related V<sub>TH</sub> distribution shifts are
minimized to improve read margins
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International; 02/2001
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Tae-Sung Jung,
Young-Joon Choi,
Kang-Deog Suh,
Byung-Hoon Suh,
Jin-Ki Kim, Young-Ho Lim,
Yong-Nam Koh,
Jong-Wook Park,
Ki-Jong Lee,
Jung-Hoon Park,
Kee-Tae Park,
Jhang-Rae Kim,
Jeong-Hyong Yi,
Hyung-Kyu Lim
[show abstract]
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ABSTRACT: For a quantum step in further cost reduction, the multilevel cell
concept has been combined with the NAND flash memory. Key requirements
of mass storage, low cost, and high serial access throughput have been
achieved by sacrificing fast random access performance. This paper
describes a 128-Mb multilevel NAND flash memory storing 2 b per cell.
Multilevel storage is achieved through tight cell threshold voltage
distribution of 0.4 V and is made practical by significantly reducing
program disturbance by using a local self-boosting scheme. An
intelligent page buffer enables cell-by-cell and state-by-state program
and inhibit operations. A read throughput of 14.0 MB/s and a program
throughput of 0.5 MB/s are achieved. The device has been fabricated with
0.4-μm CMOS technology, resulting in a 117 mm<sup>2</sup> die size
and a 1.1 μm<sup>2</sup> effective cell size
IEEE Journal of Solid-State Circuits 12/1996; · 3.23 Impact Factor
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Tae-Sung Jung,
Young-Joon Choi,
Kang-Deog Suh,
Byung-Hoon Suh,
Jin-Ki Kim, Young-Ho Lim,
Yong-Nam Koh,
Jong-Wook Park,
Ki-Jong Lee,
Jung-Hoon Park,
Kee-Tae Park,
Jang-Rae Kim,
Jeong-Hyong Lee,
Hyung-Kyu Lim
[show abstract]
[hide abstract]
ABSTRACT: The NAND flash memory was originally designed to target
solid-state mass storage applications. Key requirements of mass storage,
low cost and high serial access throughput, have been achieved by
sacrificing a non-critical feature, fast random access. For a quantum
step in cost reduction, the multi-level cell is combined with NAND flash
memory. This 128 Mb multi-level NAND flash memory stores two bits per
cell by tight programmed cell threshold voltage (Vth) control and is
made practical by significantly reducing program disturbs
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International; 03/1996
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Kang-Deog Suh,
Byung-Hoon Suh, Young-Ho Lim,
Jin-Ki Kim,
Young-Joon Choi,
Yong-Nam Koh,
Sung-Soo Lee,
Suk-Chon Kwon,
Byung-Soon Choi,
Jin-Sun Yum,
Jung-Hyuk Choi,
Jang-Rae Kim,
Hyung-Kyu Lim
[show abstract]
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ABSTRACT: While the performance of flash memory exceeds hard disk drives in
almost every category, the cost of flash memory must come down in order
to gain wider acceptance in mass storage applications. This paper
describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only
high performance but also low cost with a 94.9 mm<sup>2</sup> die size,
improved yields, and a simple process with 0.5 μm CMOS technology.
Die size is reduced by eliminating high voltage operation on the
bitlines through a self boosted program inhibit voltage generation
scheme. Incremental-step-pulse programming results in a 2.3 MB/s program
data rate as well as improved process variation tolerance. Interleaved
data paths and a boosted wordline results in a 25 ns burst cycle time
and a 24 MB/s read data rate. Maximum operating current is less than 8
mA
IEEE Journal of Solid-State Circuits 12/1995; · 3.23 Impact Factor
