Y.P. Tsividis

Columbia University, New York City, New York, United States

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Publications (85)95.12 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The filter is designed using a mix of asynchronous and real-time digital hardware, and for this reason relies on neither a clock nor the input data rate for setting its frequency response. The modular architecture of the filter, including delay segments with separated data and timing paths and a pipelined multi-way adder, allows easy extensions for different data widths. The filter was used as part of an ADC/DSP/DAC system which maintains its frequency response intact for varying sample rates without requiring any internal change. This property is not possible for any synchronous DSP system. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning, and for certain inputs, has signal-to-error ratio which exceeds that of clocked systems.
    IEEE Journal of Solid-State Circuits 10/2014; 49(10):2292-2304. DOI:10.1109/JSSC.2014.2336532 · 3.11 Impact Factor
  • Yannis Tsividis
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    ABSTRACT: I grew up in a suburb near Athens, Greece, to a middle-class family that went through very difficult times. One of my earliest memories is of an attraction to musical instruments, especially pianos, and of my parents pulling me away from them; I was later told that they were afraid I would become a musician, and that I "would starve". To this day, I regret not having learned to play an instrument well. Yet music is very much a part of my life. I credit it, in part, for my interest in radio and audio and, through those, in all things electronic.
    IEEE Solid-State Circuits Magazine 01/2014; 6(4):14-35. DOI:10.1109/MSSC.2014.2348933
  • Yannis Tsividis
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    ABSTRACT: One often reads of cases in which the confluence of several factors, key among them the presence of a core of driven individuals, attracts other motivated people and leads to a happy situation characterized by enthusiasm and creativity, where ?sparks fly?. Examples can be found in many fields, from physics (e.g., University of G?ttingen, Germany, in the 1920s) to music (e.g., Louisville Orchestra, 1950s). In engineering, one of the best examples of this can be found in the Integrated Circuits Lab at the University of California, Berkeley, in the early-to-mid-70s and beyond.
    IEEE Solid-State Circuits Magazine 01/2014; 6(2):22-24. DOI:10.1109/MSSC.2014.2313711
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    Yannis Tsividis, John Milios
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    ABSTRACT: This paper discusses equivalent-circuit modeling of the electrochemical impedance corresponding to one-dimensional diffusion in a uniform medium. It argues that, of the several equivalent circuits in use for such modeling, one – namely the nonuniform resistance–capacitance ladder – has attractive properties that are not shared by any other equivalent circuit. Explicit, analytical expressions are derived for the efficient development of this ladder equivalent, which provide advantages compared to computer optimization. Although the context of this work is battery modeling, the results presented can be of value in other fields where diffusion is studied and modeled.
    Journal of electroanalytical chemistry 10/2013; 707:156–165. DOI:10.1016/j.jelechem.2013.08.017 · 2.87 Impact Factor
  • Colin Weltin-Wu, Yannis Tsividis
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    ABSTRACT: This paper presents a clock-less 8b ADC in 130 nm CMOS technology, which uses signal-dependent sampling rate and adaptive resolution through a time-varying comparison window, for applications with sparse input signals. Input-dependent dynamic bias is used to reduce comparator delay dispersion, thus helping to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54 dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20 kHz bandwidth with 3-9 μW power from a 0.8 V supply.
    IEEE Journal of Solid-State Circuits 09/2013; 48(9):2180-2190. DOI:10.1109/JSSC.2013.2262738 · 3.11 Impact Factor
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    ABSTRACT: Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of the limitations of conventional digital and analog implementations. Per-edge digital signal encoding is used for parallel processing of continuous-time samples with a temporal spacing as narrow as 15 ps, generated by a 3-b CT flash ADC. Parallel digital delay chains and programmable charge pumps realize the asynchronous filtering operation, each consuming negligible power while awaiting a new sample. A six-tap CT ADC and CT digital FIR processor system occupies 0.07 mm2 and achieves dynamic range of over 20 dB in the 0.8-3.2-GHz signal range. The system's rate of operations automatically adapts to the signal, thus causing its power dissipation to vary in the range of 1.1 to 10 mW according to input activity.
    IEEE Journal of Solid-State Circuits 09/2012; 47(9):2164-2173. DOI:10.1109/JSSC.2012.2203459 · 3.11 Impact Factor
  • Tao Mai, Yannis Tsividis
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    ABSTRACT: We convert linear continuous-time systems based on delays to internally nonlinear ones, with unchanged input–output behavior. The internal nonlinearities can be chosen so that the internal modified noise transfer functions result in improved output signal-to-noise ratio for small inputs, thus extending the usable dynamic range. This results in companding signal processors, of which two examples are given—one using syllabic and one using instantaneous companding. This study complements earlier work on externally linear continuous-time systems with rational transfer functions and on such systems containing discrete-time delays.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 08/2012; 59(8):476-480. DOI:10.1109/TCSII.2012.2204113 · 1.19 Impact Factor
  • Aaron E. Klein, Yannis P. Tsividis
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    ABSTRACT: We present a technique for applying arbitrary in- vertible nonlinear functions to the internal signals of a prototype linear time-invariant digital signal processor, without causing any output disturbances. By using our proposed technique, the external input-output behavior of the DSP remains linear, and identical to that of the prototype, despite the nonlinear behavior of its internal signals. We explore the specific application of our technique to instantaneous companding, in which the introduced nonlinearities compress the dynamic range of the internal signals, so that the latter span most of the available bits in the system, thus improving the signal-to-noise-plus-distortion-ratio at the output, for low to medium input signal levels. We discuss the choice of nonlinear functions for this companding application, and we present an efficient hardware implementation for the standard 15-segment piecewise-linear approximation to the 255- law. We compare the performance and hardware overhead of our technique with that of other companding architectures.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2011; 58-I(11):2718-2728. DOI:10.1109/TCSI.2011.2157733 · 2.30 Impact Factor
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    ABSTRACT: We present techniques for processing MPEG-audio encoded signals during the decoding process, using efficient fixed-point arithmetic operations. A large signal-to-quantization-noise-ratio is achieved over a large range of input levels. By taking advantage of MPEGaudio built-in properties, quantization distortion at the outputs of our systems is kept largely inaudible, even though only low-resolution fixed-point operations are used in the processing.
    Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2011, May 22-27, 2011, Prague Congress Center, Prague, Czech Republic; 01/2011
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    ABSTRACT: GHz-range applications that operate in a variety of signal situations and/or multiple standards require highly programmable responses that cannot be provided by analog circuits. Conventional digital solutions suffer from aliasing, thus requiring a complicated antialiasing filter and/or extremely high clock speeds with high power dissipation. An alternative is continuous-time (CT) DSP [1], which uses level-crossing sampling [2] but without a clock. It offers activity dependent power dissipation, is alias-free and has lower EMI emissions. This technique has so far been demonstrated in the voice band [3] but cannot be pushed beyond the MHz range because it involves extremely narrow pulse widths that cannot be handled by digital logic. This work bypasses this timing problem, enabling a five-orders-of-magnitude improvement in frequency capa bility compared to [3], thus making CT DSP a candidate for wideband GHz low dynamic-range applications, such as those found in pulse radio, spectrum sens ing, and channel equalization. Presented is a 3b 6-tap CT DSP system with wide programmability that is implemented in ST 65nm technology.
    IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011
  • Mariya Kurchuk, Yannis Tsividis
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    ABSTRACT: A variable-resolution (VR) quantizer with input-activity-dependent adjustable resolution is presented. Several potential schemes are discussed; the favored scheme achieves adjustable resolution by level skipping according to the speed of the input. The advantages of a VR analog-to-digital conversion (ADC) are presented with applications in continuous-time (CT) digital signal processing systems. It is shown that a decrease in resolution for fast inputs does not corrupt the in-band spectrum while leading to a reduction in the number of samples produced by a CT ADC. The result is a significant decrease in power dissipation but without in-band performance degradation. Analysis and extensive simulations are provided. Simulations using signals in the voice band show that a power reduction of over 80% is achievable with a VR quantization.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 06/2010; DOI:10.1109/TCSI.2010.2043987 · 2.30 Impact Factor
  • Mariya Kurchuk, Yannis P. Tsividis
  • Bob Schell, Yannis Tsividis
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    ABSTRACT: Digital signal processors operating in continuous time are analyzed. We demonstrate, through analytical and simulation studies, that by operating without a sampling clock the in-band quantization error power is reduced compared to conventional discrete-time systems. We present an equivalence that facilitates the study of continuous-time digital signal processors and we explore in detail the case of single sinusoid inputs as well as inputs with a Gaussian distribution. The in-band quantization error power is shown to be lower by up to for an 8-bit system, compared to a classical, sampled one with the same resolution.
    Signal Processing 10/2009; DOI:10.1016/j.sigpro.2009.04.005 · 2.24 Impact Factor
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    Yannis Tsividis
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    ABSTRACT: Today's students can be turned on to circuits if the first lab they take is exciting and motivating. We have outlined an approach to achieving this. In addition to illustrating the many concepts taught in theory courses, this approach couples experiments to applications, and encourages students to tinker and explore. We find that a proper mix of the modern and classical approaches produces excellent results. The most unambiguous indication of success for us has been seeing the students' faces light up when their designs work for the first time, and hearing them say that this lab made them realize that EE is for them. Motivating students in this way is especially important in view of the recent trend toward decreasing EE enrollments.
    IEEE Circuits and Systems Magazine 01/2009; 9(1-9):58 - 63. DOI:10.1109/MCAS.2008.931746 · 1.70 Impact Factor
  • Bob Schell, Yannis Tsividis
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    ABSTRACT: A continuous-time system that converts its analog input to a continuous-time digital representation without sampling, then processes the information digitally without the aid of a clock, is presented. Without sampling there is no aliasing, which reduces the in-band distortion power by not aliasing into band out-of-band distortion components. The 8-bit system, fabricated in a 90 nm CMOS process, utilizes continuous delay elements as part of a programmable transversal FIR filter. The input is encoded by a delta modulator without a clock into a series of non-uniformly spaced tokens, which are processed by the digital continuous-time filter and converted to an analog output using a custom DAC that guarantees there are no glitches in the output waveform. All activity is signal driven, automatically affording dynamic power scaling that tracks input activity.
    IEEE Journal of Solid-State Circuits 12/2008; DOI:10.1109/JSSC.2008.2005456 · 3.11 Impact Factor
  • Bob Schell, Yannis Tsividis
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    ABSTRACT: A low-energy delay element based on a thyristor-like circuit is proposed that is suitable for concatenation in dense arrays in order to delay narrowly spaced burst timing information with accompanying data bits. Handshaking is built into the cell to ensure no information is lost. There is no static power dissipation aside from leakage and the energy consumption is not a function of the achieved delay. A design fabricated in a UMC 90 nm CMOS process has delays from 5 ns to 1 mus, as tuned through an analog input port, require an energy consumption of 50 fJ/delay event with a supply voltage of 1 V.
    IEEE Journal of Solid-State Circuits 06/2008; DOI:10.1109/JSSC.2008.920332 · 3.11 Impact Factor
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    Yannis Tsividis
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    ABSTRACT: When one compares today's students to those of earlier generations, the differences are striking. Yet the way most of us teach has essentially remained unchanged since the middle of the past century. No wonder, then, that our students are not attracted to electrical engineering or, among those who are, many are disappointed and just drag along, or even drop out. In this article we discuss what can be done to turn things around. Parts of this article draw on an earlier one on an introductory EE class.
    IEEE Solid-State Circuits Newsletter 02/2008; DOI:10.1109/N-SSC.2008.4785684
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    Yannis Tsividis
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    ABSTRACT: In a groundbreaking and now classic 1977 paper, Eric Vittoz and J. Fellrath meticulously characterized and developed models for devices operating in the weak inversion region, as well as a variety of circuit building blocks that could operate and exploit the exponential characteristics in this region. Their killer application -- the electronic watch -- employed techniques that are now used in a score of low-voltage, micropower applications, such as biomedical devices, hearing aids, pagers, sensor interfaces, motion detectors for pointing devices, and a variety of portable instruments. This tribute to Vittoz as an educator and industrial researcher is by Yannis Tsividis of Columbia University, an esteemed scientist and educator in his own right.
    IEEE Solid-State Circuits Newsletter 01/2008; 13(3):56-58. DOI:10.1109/N-SSC.2008.4785782
  • Atsushi Yoshizawa, Yannis Tsividis
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    ABSTRACT: In the above titled paper (ibid., vol. 42, no. 5, pp. 1090-1099, May 07), corrections were made to the schematic diagram seen in Figure 8.
    IEEE Journal of Solid-State Circuits 11/2007; 42(10):2316-2316. DOI:10.1109/JSSC.2007.907178 · 3.11 Impact Factor
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    ABSTRACT: We report an ultra-low voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm, and 26 dB of on-chip image rejection. The 3.4 mm<sup>2</sup> chip consumes 8.5 mW from a 0.5 V supply.
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007

Publication Stats

2k Citations
95.12 Total Impact Points

Institutions

  • 1983–2014
    • Columbia University
      • Department of Electrical Engineering
      New York City, New York, United States
  • 2005
    • CUNY Graduate Center
      New York City, New York, United States
  • 1992–1999
    • National Technical University of Athens
      • • School of Electrical and Computer Engineering
      • • Division of Computer Science
      Athens, Attiki, Greece
  • 1993–1996
    • Budapest University of Technology and Economics
      Budapeŝto, Budapest, Hungary
  • 1982
    • Massachusetts Institute of Technology
      • Department of Electrical Engineering and Computer Science
      Cambridge, Massachusetts, United States