Y. Karkouri

Université de Montréal, Montréal, Quebec, Canada

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Publications (5)1.83 Total impact

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    ABSTRACT: A new approach to fault analysis is presented. The authors consider multiple stuck-at-0/1 faults at the gate level. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis the authors consider frontier faults where there is at least a normal path from each faulty line to a primary output. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the authors evaluate the fault-free circuit and then propagate fault effects. Assuming that fault-free response is observed, a fault-dropping procedure is then applied to eliminate faulty conditions on lines, that are either absent or may be hidden by other faulty conditions. This method is applied to some benchmark circuits and achieves a high degree of efficiency
    IEEE Transactions on Computers 02/1994; 43(1):98-103. · 1.38 Impact Factor
  • Y. Karkouri, E.M. Aboulhamid, E. Cerny
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    ABSTRACT: A new method to generate test patterns for multiple stuck-at faults in combinational circuits is presented. All multiple faults of any multiplicity are assumed present in the circuit and one does not have to resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. The authors try to generate test conditions that propagate the effect of the target fault to primary outputs regardless the effects of other faults which might be present in the circuit. When these conditions are fulfilled, the input vector is a test for the target fault and for all multiple faults containing the target fault as component. The method used a branch-and-bound technique and includes several heuristics to enhance the performance and fault detection. Experiments performed on the ISCAS'85 benchmark circuits show that high fault coverage can be obtained at a reasonable increase in cost
    European Test Conference, 1993. Proceedings of ETC 93., Third; 05/1993
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    ABSTRACT: This paper presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in the FAN and SOCRATES algorithms to guide the search part of the algorithm and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.
    Journal of Electronic Testing 01/1993; 4:237-253. · 0.45 Impact Factor
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    ABSTRACT: A method for analyzing multiple faults in gate-level combinational circuits that does not explicitly enumerate all the multiple stuck-at faults that may be present in a circuit is presented. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis, frontier faults where there is at least a normal path from each faulty line to a primary output are considered. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the normal circuit is evaluated and the fault effects propagated. A fault dropping procedure is then applied to eliminate faulty conditions on specific lines that are either absent or permanently masked by other faulty conditions. The method is applied to some benchmark circuits, and significant speedup is observed
    Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium; 07/1991
  • Source
    Younès KARKOURI, El Mostapha ABOULHAMID
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    ABSTRACT: A new method to fault diagnosis in combinational circuits is presented. We consider multiple stuck-at-(0/1) faults at the gate level. We introduce the concept of frontier faults which reduce the number of faults to consider and are equivalent to the set of all multiple faults; however, we do not enumerate all the possible multiple faults. The diagnosis is performed in two consecutive steps. Forward propagation that determines, for each line in the circuit, its fault free value and the potential effect(s) from other faulty lines that can propagate to it. Backward implication is performed from the primary outputs toward the primary inputs and determines, given the circuit response, the value(s) carried by each line. Some of the deduced values imply that either the line is not faulty, the subnetwork driving the line contains fault(s), or the line itself is faulty. The method uses the concept of Parallel- Pattern-Multiple-Fault-Propagation which allows to analyze simultaneously bit strings of responses. It was applied to benchmark circuits from ISCAS'85 and '89 sets, to locate faulty and fault-free lines in a reasonable cost.