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P. Batude,
M. Vinet,
B. Previtali,
C. Tabone,
C. Xu,
J. Mazurier,
O. Weber,
F. Andrieu,
L. Tosti,
L. Brevard, [......],
C. Le Royer,
J-M Hartmann,
L. Sanchez,
L. Baud, V. Carron,
L. Clavelier,
G. De Micheli,
S. Deleonibus,
O. Faynot,
T. Poiroux
[show abstract]
[hide abstract]
ABSTRACT: 3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.
International Electron Devices Meeting (IEDM); 12/2011
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L. Hutin,
M. Cassé,
C. Le Royer,
J.-F. Damlencourt,
A. Pouydebasque,
C. Xu,
C. Tabone,
J.-M. Hartmann, V. Carron,
H. Grampeix,
V. Mazzocchi,
R. Truche,
O. Weber,
P. Batude,
X. Garros,
L. Clavelier,
M. Vinet,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (L<sub>G</sub>=20nm; W=30nm; T<sub>SiGe</sub>=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance (up to ×2.85 I<sub>Dlin</sub> enhancement vs. SOI, I<sub>ON</sub>=520μA/μm/I<sub>OFF</sub>=130nA/μm at L<sub>G</sub>=20nm and V<sub>DS</sub>=-1V). Moreover, an improved electrostatic integrity compared to SOI pFETs is demonstrated in c-SGOI (DIBL=120mV/V vs. 160mV/V, respectively at L<sub>G</sub>=30nm). Combined to the intrinsic |V<sub>th,p</sub>| lowering properties of c-SiGe, these characteristics qualify trigate c-SGOI as a very promising candidate for high performance pMOSFETs.
VLSI Technology (VLSIT), 2010 Symposium on; 07/2010
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L. Hutin,
M. Vinet,
T. Poiroux,
C. Le Royer,
B. Previtali,
C. Vizioz,
D. Lafond,
Y. Morand,
M. Rivoire,
F. Nemouchi, V. Carron,
T. Billon,
S. Deleonibus,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20 nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22 nm nodes. We demonstrate pFET devices with promising electrical behavior (I<sub>ON</sub> = 790 ¿A/¿m; I<sub>OFF</sub> = 60 nA/¿m @ V<sub>DS</sub> = -1.2 V; L<sub>g</sub> = 30 nm), suitable for high performance applications. Excellent SCE control is also reported down to 30 nm (DIBL = 50 mV/V), through the use of Double Gate transistors.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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P. Batude,
M. Vinet,
A. Pouydebasque,
C. Le Royer,
B. Previtali,
C. Tabone,
J.-M. Hartmann,
L. Sanchez,
L. Baud, V. Carron, [......],
F. Allain,
V. Mazzocchi,
D. Lafond,
O. Thomas,
O. Cueto,
N. Bouzaida,
D. Fleury,
A. Amara,
S. Deleonibus,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4¿ of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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V. Carron,
F. Nemouchi,
Y. Morand,
T. Poiroux,
M. Vinet,
S. Bernasconi,
O. Louveau,
D. Lafond,
V. Delaye,
F. Allain,
S. Minoret,
L. Vandroux,
T. Billon
[show abstract]
[hide abstract]
ABSTRACT: We report on the development of a metallic source and drain module for FDSOI pMOSFETs including lateral PtSi formation, Ti/TiN barrier, optimized doping conditions, controlled PtSi penetration below spacers and suitable cleaning of the PtSi surface prior to barrier deposition. Mean specific contact resistivity values lower than 2 Omega mum<sup>2</sup> have been achieved, which leads to highly performant pMOSFET devices (I<sub>on</sub> = 345 muA.mum<sup>- 1</sup>/I<sub>off</sub> = 30 nA.mum<sup>-1</sup> at -1V for 50 nm gate length).
SOI Conference, 2009 IEEE International; 11/2009
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M. Vinet,
T. Poiroux,
C. Licitra,
J. Widiez,
J. Bhandari,
B. Previtali,
C. Vizioz,
D. Lafond,
C. Arvet,
P. Besson,
L. Baud,
Y. Morand,
M. Rivoire,
F. Nemouchi, V. Carron,
S. Deleonibus
[show abstract]
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ABSTRACT: In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.
IEEE Electron Device Letters 08/2009; · 2.85 Impact Factor
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P. Batude,
M. Vinet,
A. Pouydebasque,
C. Le Royer,
B. Previtali,
C. Tabone,
L. Clavelier,
S. Michaud,
A. Valentian,
O. Thomas, [......],
A. Toffoli,
F. Allain,
P. Grosgeorges,
V. Mazzochi,
L. Tosti,
F. Andrieu,
J.-M. Hartmann,
D. Lafond,
S. Deleonibus,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect control down to L<sub>G</sub> = 50 nm. Both gains in density and performance have been studied with advanced design rules. Processing CMOS on each layer leads to an average 40% density improvement as compared to 2D standard layout.
VLSI Technology, 2009 Symposium on; 07/2009
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O. Weber,
Y. Bogumilowicz,
T. Ernst,
J.-M. Hartmann,
F. Ducroquet,
F. Andrieu,
C. Dupre,
L. Clavelier,
C. Le Royer,
N. Cherkashin,
M. Hytch,
D. Rouchon,
H. Dansas,
A.-M. Papon, V. Carron,
C. Tabone,
S. Deleonibus
[show abstract]
[hide abstract]
ABSTRACT: Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO<sub>2 </sub> gate stack were fabricated with the same process for a dual channel integration scheme. Compared to the HfO<sub>2</sub>/Si reference, X1.7 strained Si electron and X9 strained Ge hole mobility gains are demonstrated, achieving symmetric n- and p-MOSFET I<sub>Dsat </sub> performance. This X9 strained Ge hole mobility enhancement highly exceeds previous reported results on Ge pMOSFETs with high-k dielectrics. For the first time, such a hole mobility enhancement, theoretically predicted and experimentally reported with thick SiO<sub>2 </sub> gate dielectrics, is demonstrated with a thin high-k gate dielectric (EOT=14Aring)
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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A. Pouydebasque,
B. Dumont,
R. El-Farhane,
A. Halimaouit,
C. Laviron,
D. Lenoblet,
C. Rossato,
N. Casanova, V. Carron,
S. Pokrant,
T. Skotnicki
[show abstract]
[hide abstract]
ABSTRACT: In this work, we report a study of the integration of NMOS and PMOS junctions with solid phase epitaxy (SPE). For the first time, considerably improved short channel effects are demonstrated with SPE for both NMOS and PMOS (-30% / -25% in DIBL at L<sub>g</sub>=40nm for N and P devices respectively). However, a 12/15% (NMOS/PMOS) Ion degradation is observed at V<sub>d</sub>=0.9V that is explained by a contact resistance issue. Solving this contact resistance problem enables to recover the performance of spike annealed devices within 5%. Gate capacitance measurements demonstrate no significant poly-depletion degradation. Finally no degradation is reported for the poly-edge linear junction leakage and bulk-to-drain leakage. These results demonstrate the potentiality of SPE at the 45nm node and below.
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
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[show abstract]
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ABSTRACT: Combined x-ray diffraction and wafer curvature measurements during annealing of Ni thin films (13 nm) deposited on Si (001) reveal distinct stages in stress development and silicide growth. Thanks to this unique experimental setup, a clear correlation is established between force extrema at distinct temperatures and the appearance of new silicides. It is shown that the transient formation of Ni3Si2 has a strong influence on the overall stress development.
Applied Physics Letters 07/2005; 87(4):041904-041904-3. · 3.84 Impact Factor
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A. Pouydebasque,
B. Dumont,
F. Wacquant,
A. Halimaoui,
C. Laviron,
D. Lenoble,
R. El-Farhane,
B. Duriez,
F. Arnaud, V. Carron,
C. Rossato,
S. Pokrant,
F. Salvetti,
A. Dray,
F. Boeuf,
T. Skotnicki
[show abstract]
[hide abstract]
ABSTRACT: This paper demonstrates that, for NMOS, the use of LSA and smart junction engineering enable to improve dramatically short channel effects (-65% in DIBL at L<sub>g</sub>=45 nm due to lower X<sub>j</sub> and DL) and I<sub>on</sub>/I<sub>off</sub> performance (+7% I<sub>on</sub> at I<sub>off</sub>=100 nA/μm due to steeper sub-threshold slope and reduced poly-depletion) compared to spike annealed N-MOSFETs. These results show the potential advantage of ultra-high temperature and non diffusive annealing such as LSA that may be necessary for the 45 nm technology and below.
Junction Technology, 2005. Extended Abstracts of the Fifth International Workshop on; 07/2005
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D. Aime,
B. Froment,
F. Cacho, V. Carron,
S. Descombes,
Y. Morand,
N. Emonet,
F. Wacquant,
T. Farjot,
S. Jullian,
C. Laviron,
M. Juhel,
R. Pantel,
R. Molins,
D. Delille,
A. Halimaoui,
D. Bensahel,
A. Souifi
[show abstract]
[hide abstract]
ABSTRACT: A wide workfunction (Φ<sub>m</sub>) tuning range from 4.29eV to 4.99eV using total silicidation of doped polysilicon gate with nickel is presented. As, B and P but also N, Ge, Sb, In and co-implants, have been investigated to modulate the NiSi gate workfunction by dopant pile up effect at the silicide/dielectric interface. For the first time, defectivity data on dual gate oxide are presented, in correlation with the activation annealing impact and back end of line (BEOL) thermal stress effects as well as thorough TEM observations.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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F. Ducroquet,
T. Ernst,
J.-M. Hartmann,
O. Weber,
F. Andrieu,
P. Holliger,
F. Laugier,
P. Rivallin,
G. Guegan,
D. Lafond,
C. Laviron, V. Carron,
L. Brevard,
C. Tabone,
D. Bouchu,
A. Toffoli,
J. Cluzel,
S. Deleonibus
[show abstract]
[hide abstract]
ABSTRACT: The beneficial effect of double SiGe:C diffusion barriers for CMOS device downscaling is clearly demonstrated. The diffusion barriers enable to finely tailor the doping profile both in the channel and S/D regions. A drastic reduction of short channel effects down to 35nm gate length and improved I<sub>on</sub>/I<sub>off</sub> compromise have been achieved with a double carbonated barrier architecture for both nMOS and pMOS. For pMOS, reduced junction depth and lower S/D region sheet resistance are achieved with highly LDD and HDD retrograde doping profiles thanks to limited boron diffusion. For nMOS, we evidence that carbonated epi multi-layers suppress the boron pockets diffusion and therefore the roll-off effect in short gate length devices due to localised over-doping.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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B. Froment,
M. Muller,
H. Brut,
R. Pantel, V. Carron,
H. Achard,
A. Halimaoui,
F. Boeuf,
F. Wacquant,
C. Regnier, [......],
S. Lis,
V. Tirard,
P. Morin,
F. Trentesaux,
V. Gravey,
T. Mandrekar,
D. Rabilloud,
S. Van,
E. Olson,
J. Diedrick
[show abstract]
[hide abstract]
ABSTRACT: In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi<sub>2</sub> counterpart. Nickel thickness has been reduced to target the CoSi<sub>2</sub> sheet resistance. It was found that NiSi layers basic lattice planes with vertical orientation are often observed inside the grains. NiSi-based CMOS transistors show the same performance as CoSi2-transistors, but nickel can also silicide very narrow poly lines whereas cobalt can not. Moreover, NiSi reduces the STI diode-leakage perimeter, but increases channel side leakage, where CoSi<sub>2</sub> shows a "Schottky behavior". Thus we show that nickel allow MOS transistor scaling for future technology.
European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003
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M. Muller,
B. Froment, V. Carron,
A. Beverina,
R. Palla,
R. Pantel,
P. Morin,
C. Charbuillet,
A. Pouydebasque,
F. Boeuf,
T. Skotnicki
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we evaluate the potential of two concepts aiming at the vertical and horizontal reengineering of the S/D junctions of sub-50 nm-CMOS transistors: slim S/D spacers and Ni silicide. We demonstrate the benefit of the lateral spacer size reduction in terms of device performance. For the junction silicidation with Ni, we find electrically equivalent results while the silicidation depth is reduced by 50% with respect to the Co reference. This will enable the use of shallower S/D junctions giving a maximum DIBL and SCE control - an approach, which is especially interesting in combination with slim spacers.
European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003
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M. Vinet,
P. Batude,
C. Tabone,
B. Previtali,
C. LeRoyer,
A. Pouydebasque,
L. Clavelier,
A. Valentian,
O. Thomas,
S. Michaud,
L. Sanchez,
L. Baud,
A. Roman, V. Carron,
F. Nemouchi,
V. Mazzocchi,
H. Grampeix,
A. Amara,
S. Deleonibus,
O. Faynot
[show abstract]
[hide abstract]
ABSTRACT: After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650 °C). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.
Microelectronic Engineering 88(4):331-335. · 1.56 Impact Factor
