-
[show abstract]
[hide abstract]
ABSTRACT: This paper presents a fully integrated V-band 8 x 8 Butler matrix in 0.13-μm CMOS technology. Since the number of building blocks exponentially increases with the order of the Butler matrix, the constituted components, including quadrature hybrids, phase shifters, and crossovers, must be redesigned for single-chip implementation in silicon. Design equations and novel layout arrangements are described. A demonstrated 8 x 8 Butler matrix was implemented, which has the compact chip size of 1.45 x 0.93 mm<sup>2</sup>, no dc power consumption, and low average loss of 3.1 dB. Eight spatial beams with the averaged 5.9 dBi gain and 0.6<sup>°</sup> main-beam direction tolerance were obtained in 56 to 66 GHz.
IEEE Transactions on Microwave Theory and Techniques 01/2011; · 1.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A fast clutter cancellation technique is proposed for quadrature Doppler radar to robustly detect the vital signals when clutters enter the test environment. The dc offset at baseband varies with the change of test environment, dramatically reducing the accuracy of vital signal detection. To solve this problem, a clutter cancellation generator is employed in the radar receiver. Based on the detected dc offset values in I and Q channels, the generator produces an output signal, anti-phase to the received clutter signal, such that the clutter signal is cancelled at RF frontend. Therefore the time-varying dc offset at baseband is eliminated. The clutter cancellation method is described and the experiment was conducted to demonstrate the proposed method.
Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International; 06/2010
-
[show abstract]
[hide abstract]
ABSTRACT: A technique aimed at peak sidelobe level (SLL) reduction for wide-angle scanning arrays is presented in this work, based on the use of a newly designed pattern-reconfigurable antenna (PRA). The proposed antenna consists of a monopole antenna and two parasitic strips, where each strip can be reconfigured into either a reflector or a director via PIN diode switches, leading to the beam deflection. A 2.45 GHz PRA was implemented and the measured results demonstrate three reconfigurable patterns, radiating toward two end-fire and one broadside directions, respectively. When this PRA is used in a 1×4 linear array, the SLL is -7.5 dB at end-fire directions and -11.8 dB at broadside. The SLL at end-fire is 7.4 dB enhancement compared to the linear array with the conventional monopole. The design principle was discussed and a Butler-matrix-fed linear array with four PRAs was implemented for demonstration.
Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International; 06/2010
-
J. Solid-State Circuits. 01/2010; 45:2273-2282.
-
[show abstract]
[hide abstract]
ABSTRACT: A 25-GHz CMOS phased array receiver front-end with full-range beam steering is presented. The entire beam steering range is divided into five subsectors, where in each subsector the receive beam is steered by vector distribution and weighted vector combination of the received signals from array antennas. Such architecture has lower circuit complexity and less power consumption because no complicated full-range variable phase shifters and multiphase voltage-controlled oscillators, challenging in CMOS technology, are required. The implemented 0 13 ¿m CMOS phased array MMIC consumes lower than 30 mW and takes only a small area of 1.43 mm<sup>2</sup>. The measured array factors at various incident angles are demonstrated. It has 10-12 dB measured power gain and 9-10.5 dB noise figure in 24.5-26 GHz.
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian; 12/2009
-
[show abstract]
[hide abstract]
ABSTRACT: This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low- Q CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within plusmn0.6<sup>deg</sup> and amplitude balance less than plusmn 0.3 dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm<sup>2</sup>. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of plusmn0.8<sup>deg</sup> and amplitude balance of plusmn 0.3 dB over a 10% fractional bandwidth with a chip area of 0.1 mm<sup>2</sup> .
IEEE Transactions on Microwave Theory and Techniques 04/2009; · 1.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: CMOS reflection-type phase shifters with minimal insertion-loss variation over quadrants of phase-shift range are presented. Two performance enhancement techniques are proposed. First, the 3-dB quadrature hybrid is designed with a phase-compensated inductively coupled hybrid. Second, an impedance-transformed pi-resonated varactor network is presented to provide a full 360deg phase range, using a MOSFET varactor with limited reactance variation range. The design considerations and simulation are described. Two experimental 2.45-GHz phase shifters were implemented in 0.18-mum CMOS technology. One has a measured phase-shift range of 120deg with the insertion loss of 5.6 plusmn 1.2 dB in 2.33-2.60 GHz and the other has a phase range larger than 340deg with the insertion loss of 10.6 plusmn 2 dB in 2.44-2.55 GHz. Both chips are extremely compact with sizes of 0.72 and 0.66 mm<sup>2</sup>, respectively, and consume zero dc power.
IEEE Transactions on Microwave Theory and Techniques 11/2008; · 1.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: This paper presents a novel design of monolithic 2.5-GHz 4times4 Butler matrix in 0.18-mum CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Butler matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of 45plusmn3deg, 135 plusmn 4deg, -45 plusmn 3deg, and -135 plusmn 4deg with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1 X 4 monopole antenna array. The generated beams are pointing to -45deg, -15deg, 15deg, and 45deg, respectively, with less than 1deg error, which agree very well with the predictions. This Butler matrix consumes no dc power and only occupies the chip area of 1.36 times 1.47 mm<sup>2</sup>. To our knowledge, this is the first demonstration of the single-chip Butler matrix in CMOS technology.
IEEE Transactions on Microwave Theory and Techniques 09/2008; · 1.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A 24-GHz 4-way Butler matrix MMIC in 0.18-mum CMOS technology is presented. The multi-layer structure of CMOS process is utilized to monolithically realize the bulky Butler matrix on silicon substrate. Particularly, the multi-layer bifilar transformer is introduced to miniaturize the circuit and reduce the signal loss. The implemented CMOS Butler matrix MMIC only occupies a chip area of 0.41 mm<sup>2</sup> (excluding I/O pads). The experimental results show that insertion losses are 2.2plusmn0.6 dB from 23 to 25 GHz and the phase errors are within 6deg. Therefore, by connecting this Butler matrix to a linear array antenna, four orthogonal beams, pointing to -49deg, -15deg, 15deg, and 49deg, respectively, are generated within 0.3deg error.
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE; 05/2008
-
[show abstract]
[hide abstract]
ABSTRACT: A 24-GHz bi-directional CMOS reflection-type phase shifter (RTPS) with full 360deg phase tuning range and minimal insertion-loss variation is presented. Two circuit enhancement techniques are employed: the broadside-coupled transformer-based hybrid and the pi-type resonated varactor load. The implemented 0.18-mum CMOS RTPS demonstrates a measured phase shift range of 360deg with small insertion-loss variation of plusmn1.2 dB at 24 GHz. The chip is 0.33 mm<sup>2</sup> in area and it consumes zero DC power.
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE;
