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ABSTRACT: A transceiver with adaptive power control using a process and frequency monitor (PFM) is proposed. The PFM employs gain calibration with a replica voltage-controlled oscillator (VCO) and operates in the background. A five-bit digital code detected by the VCO gain calibration is applied to an adaptive-amplitude driver, an adaptive-bandwidth receiver, and an adaptive-bandwidth phase-locked loop. A test chip was fabricated in a 110-nm CMOS process and achieved adaptive power control over a wide frequency range (0.05 to 3.4 Gb/s). At data rate of 100 Mb/s, the measured power consumption attained with adaptive power control was 75% lower than that attained with a conventional architecture without adaptive power control.
IEEE Journal of Solid-State Circuits 05/2011; · 3.23 Impact Factor
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T. Ebuchi,
Y. Komatsu,
T. Okamoto,
Y. Arima,
Y. Yamada,
K. Sogawa,
K. Okamoto,
T. Morie,
T. Hirata,
S. Dosho,
T. Yoshikawa
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ABSTRACT: A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (K<sub>v</sub>) and charge-pump (CP) current over C (I<sub>CP</sub>/C), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using K<sub>v</sub> and I<sub>CP</sub>/C calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 Mbps (625 MHz) the reduction of spectrum peak amplitude is 18.6 dB which is 2.3 dB better than the reduction obtained without calibration.
IEEE Journal of Solid-State Circuits 04/2009; · 3.23 Impact Factor
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ABSTRACT: This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction (-19 dB to the non-SSC situation) and a small core area of 0.25 mm<sup>2</sup> in 0.13-mum CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm<sup>2</sup>. Moreover, it achieved good jitter tolerance (flat 0.8 UI at >1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10/2008; · 1.22 Impact Factor
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ABSTRACT: We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20- m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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ABSTRACT: A physical layer LSI has one DS-port and two βports in
accordance with IEEE1394-2000 and P1394b Draft 1.01 respectively. The
0.25 μm CMOS LSI realizes 800 Mb/s and 1.2 km peer-to-peer IEEE1394
networking through βport. Each βport requires 180 mW active
power and is treated as ASIC macro for future large system integration
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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ABSTRACT: To realize GB/s data acquisition while suppressing EMI problems,
multiport (parallel) optical interconnection is desired. In multiport
optical interconnections, a CMOS receiver core in the receiver (which
receives serial data from PD array and amplifier) must have (i) >1
Gb/s data acquisition capability with clock recovery for reception of
long data streams, (ii) asynchronous burst data acquisition capability
to avoid complicated data modulation, (iii) low power dissipation
required for multiport receiver LSIs. The authors present a prototype
chip, which is fabricated in a 0.25 μm CMOS process, to implement
these requirements
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International; 02/2000
