Siou-Shen Lin

National Taiwan University, Taipei, Taipei, Taiwan

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Publications (3)0 Total impact

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    ABSTRACT: A 5mW MPEG4 SP encoder is implemented on a 7.7mm<sup>2</sup> die in 0.18mum CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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    ABSTRACT: By exploiting the characteristics of the video signal, two content-aware decision criteria are proposed to identify the complexity of motion vectors. Based on these two decision criteria, as well as different combinations of various motion estimation algorithms, four different modes are proposed to allow the computation resources to be varied dynamically between different power constraints. The proposed decision criteria also enable the maximization of quality under each power constraint by a quality-driven diversity-based search approach. According to our simulation results, the proposed algorithm can effectively reduce the computation resources to 40%, 21%, and 3.73% with only 0.0036 dB, 0.01 dB, and 0.16 dB average quality degradation, respectively. As a result, the proposed algorithm is well-suited for video coding systems that desire a power-awareness feature.
    Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on; 11/2004
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    Siou-Shen Lin, Po-Chih Tseng, Liang-Gee Chen
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    ABSTRACT: In this paper, a novel low-power parallel tree architecture is proposed for full search block-matching motion estimation. The parallel tree architecture exploits the spatial data correlations between parallel candidate block searches for data sharing, which effectively eliminates huge amount of data access bandwidth while consumes fewer hardware resources compared with array-based architectures. Combining with adaptive parallel partial distortion elimination algorithm, the required average clock cycle count for each macroblock search can be greatly reduced to below 50% to achieve low-power operation. Besides, this architecture can also eliminate redundant computation without pipeline latency and excess power consumption caused by register shifting and redundant memory accessing in array-based architectures. The proposed architecture is suitable for high-end real-time portable video encoding system, which desires high-quality video but low-power consumption.
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004