Raymond J. Sung

University of Alberta, Edmonton, Alberta, Canada

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Publications (4)2.44 Total impact

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    ABSTRACT: We introduce a three-dimensional (3-D) processor-in-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physical 3-D communications network that can substantially reduce interconnect lengths and relieve routing congestion. The test chip, with 128 Kb of memory and 512 processing elements (PEs) on two fully depleted silicon-on-insulator (SOI) dies, can achieve a peak of 170 billion-bit-operations per second at 400 MHz.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 04/2005; · 1.22 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We introduce a three-dimensional (3-D) processor-in-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physical 3-D communications network that can substantially reduce interconnect lengths and relieve routing congestion. The test chip, with 128 Kb of memory and 512 processing elements (PEs) on two fully depleted silicon-on-insulator (SOI) dies, can achieve a peak of 170 billion-bit-operations per second at 400 MHz.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2005; 13:358-369. · 1.22 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present a three-dimensional processor-in-memory integrated circuit that provides linearly increasing processing power, while incurring no extra design effort or mask sets as the number of stacked dies increases. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The test chip, with 128 kb of memory and 512 processing elements on two fully-depleted silicon-on-insulator dies, can achieve 170 billion bit-operations per second at 400 MHz.
    Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
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    ABSTRACT: We describe the design of an embedded 128-Kb Silicon-On-Insulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25-μm fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presented. The impact of the floating body effect is investigated for both memory reads and writes. We describe threshold mismatch effects in the sense amplifier that result from the floating body voltage. Floating body effects are compared against simulated results for an SRAM designed in a 0.25-μm partially-depleted SOI process
    9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA; 01/2001

Publication Stats

23 Citations
2.44 Total Impact Points

Institutions

  • 2001
    • University of Alberta
      • Department of Electrical and Computer Engineering
      Edmonton, Alberta, Canada