Rakesh Vattikonda

Arizona State University, Phoenix, AZ, United States

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Publications (8)2.53 Total impact

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    ABSTRACT: The authors present a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation. On the basis of the reaction-diffusion mechanism, this model accurately captures the dependence of NBTI on the oxide thickness ( t <sub>ox</sub>), the diffusing species ( H or H <sub>2</sub>) and other key transistor and design parameters. In addition, a closed form expression for the threshold voltage change (DeltaV<sub>th</sub>) under multiple cycle dynamic operation is derived. Model accuracy and efficiency were verified with 180, 130 and 90 nm silicon data. The impact of NBTI on the delay degradation of a ring oscillator and the various metrics of the SRAM such as its data retention voltage, read and hold margins, as well as read and write delay, is also investigated.
    IET Circuits Devices & Systems 09/2008; · 1.02 Impact Factor
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    ABSTRACT: Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current I<sub>sub</sub>, which becomes increasingly problematic with technology scaling as various leakage components dominate I<sub>sub</sub>. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.
    IEEE Transactions on Device and Materials Reliability 01/2008; · 1.52 Impact Factor
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    ABSTRACT: The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (I<sub>sub</sub>), which becomes increasingly problematic with technology scaling as various leakage components dominate I<sub>sub</sub>. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65 nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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    ABSTRACT: This paper presents a simulation framework for reliability analysis of circuits in the SPICE environment. The framework incorporates the degradation of physical parameters such as threshold voltage (Vtp) into circuit simulation and enables the design of highly reliable circuits. The parameter degradation is based on the numerical solution for the reaction-diffusion (R-D) mechanism, which is a general model applicable to various reliability effects such as NBTI, HCI, NCS, and SEE. In particular, the accuracy and efficiency of this method was verified for NBTI degradation with 130nm experimental and simulation data over a wide range of stress voltages and temperature. The model also accurately captures the dependence of NBTI on multiple diffusion species (H/H2), key process (Vth, tox) and environmental parameters (VDD, temperature). The circuit level performance of this method is verified with silicon data from ring-oscillator circuit. We also investigated the predicted impact of NBTI on representative digital circuits
    8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA; 01/2007
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    ABSTRACT: Negative-bias-temperature-instability (NBTI) has become the primary limiting factor of circuit lifetime. In this work, we develop a general framework for analyzing the impact of NBTI on the performance of a circuit, based on various circuit parameters such as the supply voltage, temperature, and node switching activity of the signals etc. We propose an efficient method to predict the degradation of circuit performance based on circuit topology and the switching activity of the signals over long periods of time. We demonstrate our results on ISCAS benchmarks and a 65 nm industrial design. The framework is used to provide key design insights for designing reliable circuits. The key design insights that we obtain are: (1) degradation due to NBTI is most sensitive on the input patterns and the duty cycle; the difference in the delay degradation can be up to 5X for various static and dynamic conditions, (2) during dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; (3) NBTI has marginal impact on the clock signal.
    Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007; 01/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation. Based on the reaction-diffusion (R-D) mechanism, this model accurately captures the dependence of NBTI on the oxide thickness (t<sub>ox</sub>), the diffusing species (H or H<sub>2</sub>) and other key transistor and design parameters. In addition, a closed form expression was derived for the threshold voltage change (DeltaV<sub>th </sub>) under multiple cycle dynamic operation. Model accuracy and efficiency were verified with 90-nm experimental and simulation data. The impact of NBTI was further investigated on representative digital circuits
    Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
  • J. Low Power Electronics. 01/2006; 2:401-411.
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    Rakesh Vattikonda, Wenping Wang, Yu Cao
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    ABSTRACT: Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the degradation of NBTI in both static and dynamic operations. Model scalability and generality are comprehensively verified with experimental data over a wide range of process and bias conditions. By implementing the new model into SPICE for an industrial 90nm technology, key insights are obtained for the development of robust design solutions: (1) the most effective techniques to mitigate the NBTI degradation are VDD tuning, PMOS sizing, and reducing the duty cycle; (2) an optimal VDD exists to minimize the degradation of circuit performance; (3) tuning gate length or the switching frequency has little impact on the NBTI effect; (4) a new switching scenario is identified for worst case timing analysis during NBTI stress.
    Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006; 01/2006