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ABSTRACT: A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (10<sup>9</sup> multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between the LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256 times 512 array of 3-T charge-conserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated in a face detection task.
IEEE Journal of Solid-State Circuits 12/2007; · 3.23 Impact Factor
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ABSTRACT: A resonant adiabatic mixed-signal 128 times 256 array processor achieves 1.1 TMACS (10<sup>12</sup> multiply-accumulates per second) per mW of power from a 1.6 V DC supply. The 1.9 mum times 9 mum 3T NMOS unit cell with single-wire pitch multiplexed bit/compute line provides charge-conserving lb-lb multiplication and single-wire analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance variability maintaining clock oscillations near resonance.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: The mixed-signal processor performs digital vector-matrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Matrix coefficients are stored in a bit-parallel form. Delta-sigma analog-to-digital conversion of the analog array outputs is combined with oversampled unary coding of the digital inputs. Sorting of unary inputs results in at most a single input line transition for arbitrary multi-bit inputs. This amounts to a linear gain in energy efficiency of the computational array in the number of bits of the input vector. The 256 × 128 CID/DRAM processor with integrated 128 delta-sigma ADC measures 3 mm × 3 mm in 0.5 μm CMOS and delivers 6.5 GMACS dissipating 5.9 mW of power. CID/DRAM array dynamic power dissipation is reduced by a factor of four through sorting 8-bit inputs.
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
