R. Caluwaerts

imec Belgium, Louvain, Flemish, Belgium

Are you R. Caluwaerts?

Claim your profile

Publications (16)13.29 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Carbon nanotubes (CNTs) were integrated successfully into 150 nm contact holes having a TiN underlayer and a Cu single damascene top contact module. All the integration steps for CNT integration, for patterning the Cu top contact and the mask-set used are compatible with 130 nm device technologies on 200 mm wafers. The first resistance yield plots for the CNT contacts on full wafer level are presented. For CNT grown at 540 °C in contact holes with aspect ratio 1.3, a single CNT contact hole resistance of 3.4 kΩ was achieved. The structure designed, the process flow presented here for CNT integration, and the automatic probing constitute a platform that allows benchmarking different recipes and process conditions. This constitutes a significant step forward towards the realization of a contact module with vertical CNT interconnects of superior quality. This is because the platform can speed up the learning cycle time for optimizing the CNT interconnect based on learning from the electrical performance.
    Microelectronic Engineering 06/2013; 106:106–111. DOI:10.1016/j.mee.2012.09.004 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The copper interconnect technology is constrained by the significant current distribution due to the terminal effect for resistive thin seeds. As a result, the current in the wafer center can become insufficient for cathodic protection of thin copper seeds leading to center seed corrosion. To improve the current distribution, the exchange current density can be lowered e.g. by lowering the copper concentration. Our approach is to investigate and develop acid ultra-low copper baths with feature fill capability. For this goal, the optimum additives concentrations were sought and fill studies in 30 nm trenches were performed. In addition, proposing a high acid chemistry that is also compatible with direct plating, would enable the in-situ copper seed formation and filling in one and the same process step for direct plating on non-copper seed.
    Journal of The Electrochemical Society 02/2013; 160(12):D3255-D3259. DOI:10.1149/2.041312jes · 2.86 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The early detection of Cu sub-surface voids in nano-interconnects has become a main challenge with the reduction of the critical dimensions of the interconnects. A new methodology for full wafer Cu void inspection with high sensitivity and high speed has been developed using a Multi-Purpose SEM (MP-SEM) using high accelerating voltage, high resolution and multi BSE detectors. This inspection methodology has been used to evaluate the Cu metallization quality in nanointerconnects. The effectiveness of this inspection methodology was proven through the evidence of relations between Cu void density, trench widths, pattern density, and surrounding dummy structures.
    Proceedings of SPIE - The International Society for Optical Engineering 03/2012; DOI:10.1117/12.916254 · 0.20 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Scaling air-gap interconnects to 70nm pitch is demonstrated for the first time by combining air-gap technology (SiO2 etch-back and non-conformal CVD) and the double patterning approach. A capacitance reduction of 45% was measured on the air-gaps compared to the SiO2 reference. The reliability performance of the air-gaps was then evaluated and it was found that the structures exceeded 10years lifetime at 2MV/cm, almost matching the performance of SiO2 interconnects. Air-gaps could therefore make a promising low-RC solution for future technology nodes.
    Microelectronic Engineering 07/2011; 88(7):1618-1622. DOI:10.1016/j.mee.2011.03.006 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.
  • [Show abstract] [Hide abstract]
    ABSTRACT: A ternary WNxCy system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF6), triethyl borane (TEB) and ammonia (NH3) as precursors. The WCx layers were deposited by a novel ALD process at a process temperature of 250 °C. The WNx layers were deposited at 375 °C using bis(tert-butylimido)-bis-(dimethylamido)tungsten (tBuN)2(Me2N)2W (imido–amido) and NH3 as precursors. WNx grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WCx does on chemical oxide. WNxCy grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WNx. In the case of the ternary WNxCy system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WCx based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H2O2) is a potential problem. Higher resistivity values are determined for the binary WNx layers. WNx shows a constant composition and density throughout the layer.
    Microelectronic Engineering 11/2007; 84(11):2460-2465. DOI:10.1016/j.mee.2007.05.023 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A promising method to produce low-k films with a dielectric constant, k, less than 2.3, consists in using a porogen-based PECVD process in combination with UV cure for both porogen removal and thermo-mechanical properties enhancement. Aurora® ELK films with a dielectric constant of less than 2.3 and a Young's modulus of 4 GPa were obtained by careful tuning of (1) the porogen to Aurora® X precursor gas flows during deposition and (2) the subsequent UV-cure time. Process optimization is monitored by Fourier Transform InfraRed and Elastic Recoil Detection analyses. Porogen-related groups (i.e. CH2) are removed within the initial period of UV cure inducing thereby the formation of the porous network. However, the structural reorganization of the SiCO:H matrix, which leads to a mechanically stable film, requires a significantly longer time of UV curing for completion. Film overcuring causes the removal of CH3 groups leading to loss of hydrophobicity, film densification and k-value degradation. The optimized process results in films that show promising properties for future integration schemes.
    Surface and Coatings Technology 09/2007; 201:9264-9268. DOI:10.1016/j.surfcoat.2007.04.096 · 2.20 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Dual damascene self-aligned air gap structures have been fabricated through selective removal of interline plasma-damaged SiOC material using dilute HF solutions after metal CMP. The extent of the gaps was shown to be tuneable. The creation of interline air gaps through removal of damaged dielectric yielded significant capacitance reduction plus in addition dielectric reliability improvement. The via-reliability of 2 metal-build air gap structures was tested by thermal cycling and constant thermal stress. No significant difference in via reliability was observed between SiOC interconnects with and without air gaps. However, failure analysis showed weak spots near the bottom of the barrier, which could be detrimental for dual damascene reliability. These weak spots at the barrier bottom could lead to catastrophic failures in both via and lines during electromigration stressing. Moreover, process-related issues such as bottom liner undercut and copper corrosion need to be controlled more stringent before this air gap approach can be successfully implemented.
    Microelectronic Engineering 11/2006; 83(11):2150-2154. DOI:10.1016/j.mee.2006.09.025 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: As device dimensions scale down, the back-end-of-line dimensions scale down as well, which results in an increasing resistance-capacitance delay of the interconnect. In order to compensate for the increase in the capacitance part, porous low-k dielectrics have been introduced in copper interconnect technology. Due to the highly interconnected pore structure of most porous low-k materials, liquid and/or gaseous species fill the pores of the matrix during integration steps. In addition, pores give rise to surface roughness at the top-interface and at the sidewall after etch, which makes it difficult to deposit a thin, continuous barrier in narrow trenches embedded in porous low-k dielectrics. All of the above makes pore sealing a prerequisite for reliable porous low-k integration (Guedj et al., 2004). Different pore sealing techniques are under investigation. In the case of low-k materials in which the porosity is created using a porogen, the porosity creation could also be shifted to a later phase of the integration scheme; either after low-k etch (Caluwaerts et al., 2003) or after metal CMP (Fayole et al., 2004; Jousseaume et al., 2005), which is referred to as post-etch-burn-out (PEBO) and post-CMP-burn-out (PCBO), respectively. It has been demonstrated previously, that the dielectric reliability could be improved considerably by these kinds of pore sealing techniques (Tokei et al., 2004). In this paper, both integration approaches are compared for porous SiLKtrade dielectric resin (k=2.2) from The Dow Chemical Company and the effect of both integration approaches on the interline capacitance, the dielectric reliability and electromigration are investigated and discussed in more detail
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, two different air gap integration approaches are discussed in detail. Firstly, air gaps can be created using sacrificial materials, which are selectively removed through a capping layer either by wet- or dry-etching or by thermal decomposition. The second class benefits from the non-conformal deposition of different CVD dielectrics, which creates air gaps for narrow spaced lines. The benefit of air gaps in terms of capacitance reduction in multilevel interconnects is well known, therefore the authors will mainly concentrate on the challenges associated with the introduction of air gaps in interconnect systems. It will be shown that interconnect containing air gaps does not suffer more from reliability challenges than interconnects with porous low-k dielectrics. Therefore, air gaps can be considered as a viable option for the 32nm node and beyond.
    MRS Online Proceeding Library 12/2005; 914. DOI:10.1557/PROC-0914-F10-01
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The target of our investigation is the evaluation of the effect of decreasing thickness on the relative permittivity of dielectric films for high advanced interconnects of IC's. Two kinds of SiCOH-films with similar chemical composition and thickness between 70 and 830 nm were deposited by spin coating ("SOD") or PECVD ("CVD") on silicon wafers. The relative permittivity was determined by CV-measurement and its components of polarization response are deduced from ellipsometric and FTIR measurements. (c) 2005 Elsevier B.V. All rights reserved.
    Microelectronic Engineering 12/2005; 82(3-4, SI):405-410. DOI:10.1016/j.mee.2005.07.023 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.
    Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The effect of trace oxygen on the annealing of Cu/Ta(N)/SiO2/Si(001) damascene structures was studied. The dry oxidation of copper was investigated by annealing the wafers at 420 °C for 20 min in N2 ambients with oxygen concentrations ranging from 0 to 2500 ppm in a Rapid Thermal Processing (RTP) system. Electron Backscattered Diffraction (EBSD) mapping (also called ‘Orientation Imaging Microscopy’ (OIM)) and high resolution Scanning Electron Microscopy (SEM) were used to determine the structure, texture and chemical composition of the annealed copper. For low oxygen contents, the oxidation of the surface in bonding areas is initiated at the grain boundaries and on (111) oriented grains. The oxidation is selective and depends on the segregation of sulphur at the surface of grains with a specific orientation. For higher oxygen concentrations, the oxidation occurs readily and is dependent on the trench geometry, increasing with decreasing line width. In this case, the dimensions, the distribution of impurities in the trenches, and the microstructure of the copper modify the oxidation rate in the small features.
    Microelectronic Engineering 10/2002; DOI:10.1016/S0167-9317(02)00771-2 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The feasibility of integrating a SiLK* Semiconductor Dielectric film (*trademark of The Dow Chemical Company) that contains closed pores was studied using a single damascene test vehicle. The study focussed on tool qualification, process set-up and single damascene feasibility to demonstrate technology extendibility. The results indicate that only minor changes have to be made to the process conditions when transitioning from a dense to a porous SiLK* film.
    Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International; 02/2001
  • [Show abstract] [Hide abstract]
    ABSTRACT: The feasibility of integrating a low permittivity spin-on hardmask (SoHM) into a Cu dual damascene structure using SiLK* Semiconductor Resin (*trademark of The Dow Chemical Company) has been investigated. The study focussed on the replacement of the embedded etch stop deposited by chemical vapor deposition (CVD) by a low permittivity inorganic film deposited by traditional spin coating. The evaluation was performed using an existing damascene test vehicle. The etch selectivity was evaluated by applying different SoHM thicknesses and etch times. The patterning chemistry used was O<sub>2</sub>/N<sub>2</sub> based, in a high density TCP etch tool. The electrical data collected indicated no significant yield difference when using an embedded SoHM. The integrated k value of the SoHM film is 3.2, as compared to ~4.0 for SiO<sub>2</sub> films
    Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International; 02/2001