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ABSTRACT: A novel impulse radio (IR) ultra wideband (UWB) pulse generator (PG) intended for RFID tags is presented. A new pulse-shaping approach suited for CMOS implementation is proposed. The power consumption and chip area are reduced compared to the conventional higher order Gaussian PGs. The proposed PG uses digital gates for timing achieving good power efficiency and, meanwhile, acceptable spectral filling. The circuit is scalable both in bandwidth and center frequency. The PG is designed in a TSMC 90 nm CMOS technology. Post-layout simulations show a worst-case power consumption from a 1.2 V supply to be 6.5 pJ/pulse for a 100 MHz pulse repetition frequency (PRF). The chip area is 0.00079 mm<sup>2</sup> (38.2 μm × 20.8 μm) for the PG core.
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on; 01/2011
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ABSTRACT: We present a reconfigurable linear threshold element which may be used to implement the Boolean functions NOR3, CARRYmacr and NAND3. Pseudo floating-gate transistors are used in order to set the appropriate current-level for low-voltage operation and initial voltages are reset on the input in order to reconfigure the threshold element. Several of the blocks may be used to implement any Boolean function
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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ABSTRACT: In this paper we present a new circuit biasing scheme using very high impedance elements. The biasing scheme is used to control the gate voltage of pseudo floating-gate transistors, which may be used to build low-voltage/low-power systems. In order to demonstrate the biasing scheme a highly tunable second order section is presented.
Biomedical Circuits and Systems, 2004 IEEE International Workshop on; 01/2005
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ABSTRACT: This paper presents a flexible biasing-method for floating gate circuits. The biasing technique preserves the floating gate nature of the well known floating gate modules at the same time as it provides an effective way to adjust the gate bias level continuously. Accurate adjustment of the gate voltage is essential to handle process and temperature variation. The method also makes it very easy to quickly tune the floating gate modules dynamically. The bias technique is based on the use of controllable current sources. A delay cell based on a pseudo floating-gate all-pass-filter intended used in a low-power delay line for medical real-time 3D ultrasound imaging system has been design for proof of concept. The biasing method is believed to take analog floating-gate circuits one step closer to commercial acceptance.
Biomedical Circuits and Systems, 2004 IEEE International Workshop on; 01/2005
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ABSTRACT: In this paper, a low-voltage two pseudo-floating gate transistor all-pass filter is presented. The filter has adjustable phase-shift and only one filter capacitor. The filter operates at a supply voltage below 1 V and may have a power consumption below 160 nW. Simulation results for variable phase-shifts using Bsim3v3 are presented. The cut-off frequency or phase-shift of the filter is highly tunable.
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on; 08/2004
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ABSTRACT: We present a low-voltage/low power second order filter. The filter consists of 6 pseudo floating-gate transistors operated in weak inversion. The filter is suitable for any kind of application requiring low frequency ranges, such as biomedical products. An electronic cochlea consisting of replicas of the filter is presented. The filter operates at a supply voltage below 1 V, consumes power down to 5 nW, and has a harmonic distortion suppression of -60 dB.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on; 06/2003
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ABSTRACT: In this paper we present two novel floating-gate multiple-valued (MV) to binary converters for use in multiple-valued (MV) digital CMOS design. The first radix-R to binary converter converts an MV signal directly to a binary representation while the second converter converts a radix R/2 MV signal stepwise through a radix R/2 MV signal. Simulated data of both binary to radix 8 and radix 8 to binary converters are provided.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
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ABSTRACT: In this paper we present a novel floating-gate multiple-valued (MV) to binary converters for use in multiple-valued (MV) digital CMOS design. The MV converter is usable for producing binary outputs of MV systems and to restore or refresh MV signals. New and more simple FGUVMOS gates compared to previous presented are described. The converter converts a radix R MV signal stepwise through a radix R/2 MV signal. Simulated data of both binary to radix 8 and radix 8 to binary converters are provided.
Electronics, Circuits and Systems, 2002. 9th International Conference on; 02/2002
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ABSTRACT: In this paper, we present a novel floating-gate binary to multiple-valued converter for use in multiple-valued (MV) digital CMOS design. Techniques for reducing power supply noise are addressed and a binary to 4 bit (radix 16) MV converter is discussed. The converter has been sent for fabrication and measured results should be available. Simulation results obtained from Matlab and SpectreS are presented.
Electronics, Circuits and Systems, 2002. 9th International Conference on; 02/2002
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ABSTRACT: Presents a six transistor fully differential dual-ended low-voltage (ULV) FGUVMOS operational transconductance amplifier (FGUVMOS-OTA), and a Gm-C filter where the FGUVMOS-OTA is used. The OTA has rail-to-rail operation. A basic Gm-C filter implemented with the OTA is presented. The cut-off frequency of the filter is tunable over almost 6 decades with a supply voltage below 1 V.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
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ABSTRACT: In this paper we present a novel floating-gate (FG) multiple-valued (MV) CMOS adder. With the MV adder we can reduce the number of transistors required for adding two signals with a specific resolution. Furthermore, the MV adder is low-power due to the reduced number of transistors and the delay through a ripple adder can be reduced compared to conventional binary logic due to the reduced number of gates for the carry propagation. A binary to MV converter and a MV to binary converter are presented. Simulation data are obtained using the spectreS simulator. The chip has been sent for fabrication and measurements will be provided at the conference.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
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ABSTRACT: Ultra-low-voltage (ULV) floating-gate differential amplifiers are
presented. In this paper, we present several different approaches to
CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance
amplifiers are described. Measured results are provided
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 02/2001;
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ABSTRACT: A programming technique for controlling the floating gates (FGs)
in ultra-low-voltage (ULV) floating-gate circuits is presented. Simple
ULV PG current-scaling and level-shifting circuits are discussed. The
current scaling and level shifting are accomplished using only minimum
sized transistors and floating capacitors. Floating-gate current
multiplier and divider circuits are described. Measured results are
provided,
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 02/2001;
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ABSTRACT: In this paper we present a floating-Gate differential amplifier
input stage with tunable gain. The input stage can be used in a
differential ultra low-voltage (ULV) floating gate (FG) transconductance
amplifier. Measured data for the subcircuits operating at 0.8 V, 0.5 V
and 0.3 V are provided
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on; 02/2001
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ABSTRACT: Presents two new, reconfigurable multifunction floating-gate
circuits to produce either the inverted carry function for a full-adder,
an inverter, or two-input NAND or NOR gates. The circuits contains two
MOSFETs and three or four capacitively coupled input signals. SPICE
simulations are shown, demonstrating the principal operation, together
with preliminary measurements indicating that the circuit might operate
with a supply voltage below 100 mV
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on; 02/2001
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ABSTRACT: We present some fundamental aspects on how UV-programmed
floating-gate (FGUVMOS) circuits may be simulated using the AIM-Spice or
Eldo simulators and the BSIM3v3 model. We introduce ways of implementing
FGUVMOS binary logic simpler than previously reported. Reduction in
transistor and capacitor count for some simple NAND and NOR gates are
from three to two MOSFETs, and four to three capacitors, respectively.
We also show some aspects of a reconfigurable two-transistor circuit
capable of computing the CARRY' function for a FULL-ADDER using two
MOSFETs, which is more than 90 percent reduction in transistor count
compared to earlier reported FGUVMOS circuits
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on; 02/2001
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ABSTRACT: Presents an ultra low-voltage (ULV) floating-gate (FG)
transconductance amplifier. The amplifier can operate at supply voltages
down to 0.3 V in a standard digital double poly CMOS process. The
amplifier consists of three subcircuits, the single input analog FG
inverter, the additive (double input) analog FG inverter with tunable
gain and a FG digital inverter. Simulated data for the transconductance
amplifier is provided. Preliminary measurements of the subcircuits are
provided
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on; 02/2001
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ABSTRACT: We present a novel ultra low-voltage floating-gate
transconductance amplifier with tunable gm. The OTA can provide a sinh
shaped output current, a tanh shaped output current or an enhanced
linear sinh{tanh} output current
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on; 02/2000
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ABSTRACT: We present a novel floating-gate ultra low-voltage (ULV) analog
multiplicator with tunable linear range. Rail to rail operation is
provided in the symmetric analog “gates” presented which are
utilized in the ULV analog multiplier described in this paper
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on; 02/2000
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ABSTRACT: In this paper we describe ultra low-voltage (ULV) rail-to-rail
CMOS TANH shaped transconductance amplifiers using floating gates. The
OTA can operate with a supply voltage down to 200 mV. Preliminary
simulation results of the differential ULV amplifier are provided
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on; 02/2000
