-
[show abstract]
[hide abstract]
ABSTRACT: Multiway Decision Graphs (MDGs) are a canonical representation of a subset of many-sorted first-order logic. It generalizes
classical BDDs with abstract data and uninterpreted functions. In this paper, we describe a new MDG construction based on
the Generalized-If-Then-Else (GITE) operator. Consequently, we review the main algorithms used for verification techniques
i.e. relational product and pruning by subsumption. Unlike an earlier version of the MDG package, basic MDG algorithms are
defined uniformly through this single GITE operator which will lead to a more efficient implementation. The new tool, called
NuMDG, accepts an extended SMV language, supporting abstract data sorts.
08/2008: pages 228-242;
-
[show abstract]
[hide abstract]
ABSTRACT: Body sensor network (BSN) is a wireless network of implantable and/or wearable smart sensors. They can be deployed in medical applications, such as patients monitoring inside or outside hospital environment, as well as in high performance professional sports and other non human related applications. The size of a sensor node and its power consumption are major challenges in the design of implantable BSNs. The focus of this paper is to propose the definition of a new light weight communications protocol for the BSNs applications using very small sensor nodes supporting ultra low energy consumption.
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on; 07/2008
-
[show abstract]
[hide abstract]
ABSTRACT: In order to overcome the limitations of automated tools and the cumbersome proof process of interactive theorem proving, we adopt a hybrid approach for formal hardware verification which uses the strengths of theorem proving (HOL) with powerful mathematical tools such as induction and abstraction, and the advantages of automated tools (MDG) which support equivalence checking and model checking. The MDG system is a decision diagram based verification tool, primarily designed for hardware verification. HOL is a theorem prover built on higher-order logic. The methodology used to link the tools and the functioning of the interface are described in detail. We use the timing block of the 4 by 4 Fairisle ATM switch fabric to illustrate the verification using this hybrid tool.
07/2000;
-
[show abstract]
[hide abstract]
ABSTRACT: In order to overcome the limitations of automated tools and the cumbersome proof process of interactive theorem proving, we adopt a hybrid approach for formal hardware verification which uses the strengths of theorem proving (HOL) with powerful mathematical tools such as induction and abstraction, and the advantages of automated tools (MDG) which support equivalence checking and model checking. The MDG system is a decision diagram based verification tool, primarily designed for hardware verification. HOL is a theorem prover built on higher-order logic.
04/2000;
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we present several techniques for modeling and
formal verification of the Fairisle asynchronous transfer mode (ATM)
switch fabric using multiway decision graphs (MDGs). MDGs represent a
new class of decision graphs which subsumes Bryant's reduced ordered
binary decision diagrams (ROBDDs) while accommodating abstract sorts and
uninterpreted function symbols. The ATM device we investigated is in use
for real applications in the Cambridge University Fairisle network. We
modeled and verified the switch fabric at three levels of abstraction:
behavior, and register transfer level (RTL) and gate levels. In a first
stage, we validated the high-level specification by checking specific
safety properties that reflect the behavior of the fabric in its real
operating environment. Using the intermediate abstract RTL model, we
hierarchically completed the verification of the original gate-level
implementation of the switch fabric against the behavioral
specification. Since MDGs avoid model explosion induced by data values,
this work demonstrates the effectiveness of MDG based verification as an
extension of ROBDD-based approaches. All the verifications were carried
out automatically in a reasonable amount of CPU time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 08/1999; · 1.27 Impact Factor
-
IEEE Transactions on CAD of Integrated Circuits and Systems. 01/1999; 18(17):955 - 972.
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we present the verification of a multiprocessor
system with shared memory, using VIS tool. This system consists of three
processors; each one has its cache and all share the main memory and the
bus. Its RTL-level design is described in Verilog-HDL and the properties
to be verified, in CTL. Also, we establish the effect of data width upon
the reachability analysis. As results, safety and liveness properties
are fulfilled by the system design, and a fast increase of reachable
state number and BDD (Binary Decision Diagram) size is observed when the
data width or the processor number are growing. By using MDG tool, we
plan to resolve the negative effect of cache size increase
Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on; 02/1998
