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H. Darabi,
P. Chang,
H. Jensen,
A. Zolfaghari,
P. Lettieri,
J.C. Leete,
B. Mohammadi,
J. Chiu,
Qiang Li,
Shr-Lung Chen, [......],
P. Kilcoyne,
H. Vinh,
E. Raith,
M. Koscal,
A. Hukkoo,
C. Hayek,
V. Rakhshani,
C. Wilcoxson, M. Rofougaran,
A. Rofougaran
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ABSTRACT: A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on the radio portion mostly, and addresses the challenges of realizing a complete GSM/EDGE SoC with the RF integrated along with the rest of digital baseband circuitry. Several circuit level as well as architectural techniques are presented to realize a very low-cost and low-power 2.5G radio while meeting the stringent cellular requirements with wide margin. The radio draws a battery current of 49 mA in the receiver-mode, and 86/77 mA in the GMSK/8PSK transmit-mode. The low-IF receiver achieves a sensitivity of -110 dBm at the antenna, corresponding to a noise figure of 2.4 dB at the device input. The 8PSK±400 kHz modulation mask is - 64.1/62.7 dBc for high/low bands, with an RMS EVM of 2.45/1.95%. The radio core area is 3.95 mm<sup>2</sup> .
IEEE Journal of Solid-State Circuits 05/2011; · 3.23 Impact Factor
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C.P. Lee,
A. Behzad,
B. Marholev,
V. Magoon,
I. Bhatti,
D. Li,
S. Bothra,
A. Afsahi,
D. Ojo,
R. Roufoogaran, [......],
S. Mak,
J. Castaneda,
K. Kim,
Zhenhua Liu,
S. Bouras,
K. Chien,
V. Chandrasekhar,
P. Chang,
E. Li,
Zhimin Zhao
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ABSTRACT: A fully integrated SoC compliant with 802.11 a/b/g/ssn, BT, and FM standards is presented. Shared blocks include LNA, PA, crystal, bandgap, and RCAL. The WLAN, BT, and FM receivers achieve sensitivities better than -76 dBm (54 Mb/s/2.4 Ghz), -91 dBm, and 1 uV<sub>rms</sub>, respectively. The WLAN and BT transmitters achieve linear output powers of 21 dBm and 10 dBm, respectively.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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ABSTRACT: This paper presents a novel active blocker rejecting RF (ABR-RF) front end for RF identification (RFID) applications. The proposed ABR-RF injects the blocker replica within the low-noise amplifier of the RFID receiver chain, through a feed-forward path to actively create an arbitrary narrowband notch filtering for the in-band blockers, while not affecting the gain of the desired signal. The in-band blocker is from the leakage of the RFID self-transmitter because RFID systems use backscattering communication. The notch frequency of the ABR-RF is always locked to the RFID transmitter frequency without any passive element tuning. Fabricated in a 0.18- mum CMOS technology, the prototype improves the ABR-RF's 1-dB compression point by greater than 18 dB, and achieves a 50-dB signal-to-blocker ratio improvement. The receiver path draws 40 mA from a 1.8-V supply voltage. The blocker filtering path adds maximum of 16 mA to reject a maximum in-band blocker of 20 dBm. The die area is 1.8 times 1.2 mm<sup>2</sup>.
IEEE Transactions on Microwave Theory and Techniques 06/2009; · 1.85 Impact Factor
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A. Zolfaghari,
H. Darabi,
H. Jensen,
J. Leete,
B. Mohammadi,
J. Chiu,
Qiang Li,
Zhimin Zhou,
P. Lettieri,
Yuyu Chang, [......],
J. Castaneda,
J. Kim,
H. Tran,
P. Kilcoyne,
R. Chen,
B. Lee,
B. Zhao,
B. Ibrahim, M. Rofougaran,
A. Rofougaran
[show abstract]
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ABSTRACT: This article reviews transmitter topologies for radio transceivers with emphasis on cellular applications. In the first section it discusses different architectures and the challenges in practical implementations. Then it presents a transmitter as part of a fully integrated transceiver for GSM/GPRS/EDGE.
IEEE Communications Magazine 10/2008; · 3.79 Impact Factor
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A. Afsahi,
J.J. Rael,
A. Behzad,
Hung-Ming Chien,
M. Pan,
S. Au,
A. Ojo,
C.P. Lee,
S.B. Anand,
K. Chien, [......],
Ning Li,
E. Blecker,
J. Lin,
T. Kwan,
R. Zhu,
M. Chambers, M. Rofougaran,
A. Rofougaran,
J. Trachewsky,
P. Van Rooyen
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ABSTRACT: A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single weight combiner (SWC) system. A new signal-path Cartesian phase generation and combination technique is proposed that shifts the RF signal in 22.5deg phase steps. A 3 dB improvement in received SNR is achieved in comparison to the single path receiver. The radio and AFE occupy 10 mm<sup>2</sup> of area in a digital 0.13 mum CMOS process of which 0.29 mm<sup>2</sup> is occupied by the SWC RF receiver. The radio+AFE consume 85 mW of power in active Rx mode of which 30 mW is utilized by the SWC RF front-end.
IEEE Journal of Solid-State Circuits 06/2008; · 3.23 Impact Factor
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ABSTRACT: This paper presents an RF identification (RFID) system with a fully integrated transponder. To enable the on-chip integration of the tag's antenna, it is suggested to employ near-field coupling at high-frequency ranges, i.e., the UHF band. The RFID system including the reader and key blocks of the transponder is designed and fabricated in a standard CMOS 0.18-mum process. The system operates at 900 MHz with the coverage range of over 0.4 cm. The tag's antenna is integrated on-chip without using any special process. The reader employs multiple coils to increase its coverage area. Using a proper output network, the reader can deliver a current of 225 mA (rms) to its coil, which is designed on a printed circuit board.
IEEE Transactions on Microwave Theory and Techniques 06/2008; · 1.85 Impact Factor
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H. Darabi,
A. Zolfaghari,
H. Jensen,
J. Leete,
B. Mohammadi,
J. Chiu,
T. Li,
Z. Zhou,
P. Lettieri,
Y. Chang, [......],
J. Castaneda,
J. Kim,
H. Tran,
P. Kilcoyne,
R. Chen,
B. Lee,
B. Zhao,
B. Ibrahim, M. Rofougaran,
A. Rofougaran
[show abstract]
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ABSTRACT: This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into a single CMOS chip. Compared to the published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves a superior receive and transmit performance, and yet has up to 2x lower receive power consumption, a key requirement in cellular applications.
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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ABSTRACT: A two-point modulation technique is presented that improves the performance of nonlinear power amplifiers (PAs) in polar transmitters. In this scheme, the output amplitude modulation is performed by controlling the current of the PA. The current control technique enables the PA to provide wideband amplitude modulation, as well as high power control dynamic range. In addition, the supply voltage of the PA is adjusted based on the output power level. The voltage supply adjustment substantially improves the effective power efficiency of the PA. The voltage supply control is performed using a second-order sigma-delta dc-dc converter, which presents an efficiency of over 95% in its operational range. The PA operates at 900 MHz with maximum output power of 27.8 dBm and power efficiency of 34% at maximum output power. The proposed PA achieves 62-dB power control dynamic range with amplitude modulation bandwidth of over 17.1 MHz. The circuits are fabricated in a CMOS 0.18 mum process with a 3.3-V power supply.
IEEE Transactions on Microwave Theory and Techniques 02/2008; · 1.85 Impact Factor
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A. Behzad,
K.A. Carter,
Hung-Ming Chien,
S. Wu,
Meng-An Pan,
C.P. Lee,
Qiang Li,
J.C. Leete,
S. Au,
M.S. Kappes, [......],
A. Rofougaran, M. Rofougaran,
J. Trachewsky,
T. Moorti,
R. Gaikwad,
A. Bagchi,
J.S. Hammerschmidt,
J. Pattin,
J.J. Rael,
B. Marholev
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ABSTRACT: 802.11n is the latest offering from the IEEE standard committee tasked with enabling and enhancing WLAN systems. This standard utilizes several techniques to offer a much larger rate versus range than the legacy WLAN systems. A single-chip multiband direct-conversion CMOS MIMO transceiver (2times2) targeted for WLAN applications is presented. This transceiver is capable of satisfying the requirements of the draft 802.1 In standard and achieves PHY rates of > 270 Mb/s. The receivers and transmitters achieve an EVM of better than -41 dB (0.9%) and -40 dB (1.0%) operating in legacy g and a modes, respectively. From a 1.8 V supply and with both cores operating, the chip draws 275 mA in RX mode and 280 mA in TX mode.
IEEE Journal of Solid-State Circuits 01/2008; · 3.23 Impact Factor
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ABSTRACT: This paper presents an RFID system with fully integrated transponder. The transmit path of the reader as well as key blocks of the tag is designed and fabricated in standard CMOS 0.18 mum process. The system operates at 900 MHz with the coverage range of more than 0.4 cm. The tag's antenna is integrated on chip without using any special process. The reader employs a coil switching technique to increase its coverage area. The PA in the transmit path of the reader is designed using digital to RF configuration. By employing a proper output network, the PA can deliver a current of 225 mA (RMS) to the reader's coil.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
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ABSTRACT: This paper presents integrated blocker filtering RF front-ends (BF-RF). In wireless cellular systems the blockers are from either self transmitters, such as WCDMA or form the other users' transmitters such as GSM. The proposed blocker filtering deploys the concept of blocker injection through feedforward or feedback paths to create arbitrary narrowband notches for the out-of-band blockers, while not affecting the gain of the desired signal. The BF-RF obviates the use of the off-chip SAW filters. Fabricated in a 0.18 mum CMOS technology the prototype achieves a 50 dB of signal to blocker ratio. The receiver path draws 24 from a 1.8 V voltage supply, and the blocker filtering path adds on average only 2 mA to the total power consumption. The die area is 1.5times1.2 mm<sup>2</sup>.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
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ABSTRACT: This paper presents a guideline to design and optimize a power harvester circuit for an RF identification transponder. A power harvester has been designed and fabricated in a CMOS 0.18- process that operates at the UHF band of 920 MHz. The circuit employs an impedance transformation circuit to boost the input RF signal that leads to the improvement of the circuit performance. The power harvester has been optimized to achieve maximum sensitivity by characterizing both the impedance transformation network and the rectifier circuit and choosing the optimum values for the circuit parameters. The measurement results show sensitivity of 14.1 dBm for dc output voltage of 1 V and the output current of 2 mum that corresponds to the output power of 2 muW.
IEEE Transactions on Microwave Theory and Techniques 07/2007; · 1.85 Impact Factor
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B. Marholev,
M. Pan,
E. Chien,
L. Zhang,
R. Roufoogaran,
S. Wu,
I. Bhatti,
T.-H. Lin,
M. Kappes,
S. Khorram, [......],
H. Jensen,
H. Kim,
P. Lettieri,
S. Mak,
J. Lin,
Y.C. Wong,
R. Lee,
M. Syed, M. Rofougaran,
A. Rofougaran
[show abstract]
[hide abstract]
ABSTRACT: A low-power single-chip Bluetooth EDR device is realized using a configurable transformer-based RF front-end, a low-IF receiver and direct-conversion transmitter architecture. It is implemented in a 0.13mum CMOS process and occupies 11.8mm<sup>2</sup>. Sensitivity for 1, 2 and 3Mb/s rates is -88, -90, and -84dBm and transmitter differential EVM is 5.5% rms.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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ABSTRACT: A UHF RFID reader that handles RFID tag information as weak as -80dBm along with large inband blockers as large as 20dBm is presented. Fabricated in a 0.18mum CMOS process, the reader selectively attenuates large inband blockers, 40 to 250kHz away from the tag information, by better than 30dB using the limiting concept, while amplifying the tag information by 18dB.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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ABSTRACT: A novel switching power amplifier based on the concept of digital to analog converter (DAC) is presented for polar transmitter architecture. The novel idea in this amplifier is to generate a current proportional to the amplitude modulation signal and the power control bits. The current is then up-converted to the frequency of interest using switching transistors. In this paper, we demonstrate that the performance of the proposed circuit is superior compare to the existing power amplifiers designed for polar transmitter. The measurement results show maximum output power of 27.8dBm with power efficiency of 34%. Moreover, the amplifier exhibits amplitude modulation bandwidth of 4.2MHz and 62dB power control dynamic range. The circuit is fabricated in CMOS 0.18mum process with 3.3V power supply
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
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ABSTRACT: Next-generation wireless networks will support a wide range of data rates over several frequency bands and require adaptive and programmable system resources. Radio transceivers used in these wireless networks will incorporate self-calibration and full programmability to support their high performance and adaptivity. Low power designs at the circuit architectural, and overall system levels will enable longer battery life for portable devices. Many additional challenges exist in implementing high data rate programmable orthogonal frequency division multiplexing (OFDM) multiple-input/multiple-output (MIMO) radio transceivers that cover different frequency bands, maintain low current consumption, and are low cost. This article is an examination of the challenges in implementing high data rate programmable orthogonal frequency division multiplexing multiple-input/multiple-output radio transceivers that cover different frequency bands, maintain low current consumption, and are low cost.
IEEE Microwave Magazine 04/2005; · 2.11 Impact Factor
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ABSTRACT: Phase noise of the Fractional-N synthesizer depends critically on the linearity of its building blocks. In this research, new design methods are shown to directly improve its linearity. This includes a new re-timing scheme that effectively reduces phase noise for multi-modulus dividers. Further reductions in phase noise result from introduction of a high linearity CMOS charge pump. Measurement results verify the concept and demonstrate low phase noise performance at 4GHz.
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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H. Darabi,
S. Khorram,
Hung-Ming Chien,
Meng-An Pan,
S. Wu,
S. Moloudi,
J.C. Leete,
J.J. Rael,
M. Syed,
R. Lee,
B. Ibrahim, M. Rofougaran,
A. Rofougaran
[show abstract]
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ABSTRACT: A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46
mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It
includes all the receive and transmit building blocks, such as frequency
synthesizer, voltage-controlled oscillator (VCO), power amplifier, and
demodulator. The receiver uses a low-IF architecture for higher level of
integration and lower power consumption. It achieves a sensitivity of
-82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of
-7 dBm. The direct-conversion transmitter delivers a GFSK modulated
spectrum at a nominal output power of 4 dBm. The on-chip voltage
controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz
offset
IEEE Journal of Solid-State Circuits 01/2002; · 3.23 Impact Factor
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ABSTRACT: An FSK demodulator intended for use in Bluetooth is implemented in
a 0.35 μm CMOS process. The entire demodulator, integrated as a part
of a low-IF receiver with 2 MHz intermediate frequency, consumes 3 mA
from 2.7 V supply. The required signal-to-noise ratio (SNR) for 0.1% bit
error rate (BER) is about 18 dB
Custom Integrated Circuits, 2001, IEEE Conference on.; 02/2001
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H. Darabi,
S. Khorram,
E. Chien,
M Pan,
S Wu,
S. Moloudi,
J.C. Leete,
J. Rael,
M. Syed,
R. Lee,
B. Ibrahim, M. Rofougaran,
A. Rofougaran
[show abstract]
[hide abstract]
ABSTRACT: A fully-integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7 V supply. The receiver has -80 dBm sensitivity at 0.1% BER, and -7 dBm IIP3. The transmitter delivers a GFSK modulated spectrum at 5 dBm output power
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International; 02/2001
