Publications (4)0 Total impact
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Chapter: RuleBase: Model checking at IBM
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ABSTRACT: RuleBase is a symbolic model checking tool, developed by the IBM Haifa Research Laboratory. It is the result of four years of experience in practical formal verification of hardware which, we believe, has been a key factor in bringing the tool to its current level of maturity. Our experience shows that after a short training period, designers can operate the tool independently and achieve impressive results. We present the tool and summarize our development and usage experience, focusing on some work done during 1996.04/2006: pages 480-483; -
Conference Proceeding: Combining system level modeling with assertion based verification
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ABSTRACT: Assertion based verification (ABV) using the PSL language is currently gaining acceptance as an essential method for functional verification of hardware. A basic technique to implement ABV is to embed temporal assertions in RTL code. The paper describes the use of a PSL-based ABV methodology in a C++-based system level modeling and simulation environment. We describe the considerations of porting a tool, which translates PSL to VHDL/Verilog, to support C++, a language which was designed for software and does not have concurrent language constructs. The translation scheme is shown to be adaptable to all C-based environments. We exemplify the wide applicability of this scheme by detailing its successful deployment in a SystemC-based industrial system-on-chip (SoC) project.Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on; 04/2005 -
Article: RuleBase: Model Checking at IBM
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ABSTRACT: RuleBase is a symbolic model checking tool, developed by the IBM Haifa Research Laboratory. It is the result of four years of experience in practical formal verification of hardware which, we believe, has been a key factor in bringing the tool to its current level of maturity. Our experience shows that after a short training period, designers can operate the tool independently and achieve impressive results. We present the tool and summarize our development and usage experience, focusing on some work done during 1996.12/1999; -
Conference Proceeding: Formal verification analysis of load-voltage power dynamics and control
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ABSTRACT: Not AvailableWorld Automation Congress, 2004. Proceedings;