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Microprocessors and Microsystems - Embedded Hardware Design. 01/2010; 34:49-61.
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ABSTRACT: As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry due to the rapid increasing rate of radiation-induced soft errors while the SoC fabrication enters the very deep submicron technology. Therefore, the SoC dependability becomes a critical issue in safety-critical applications. Validating such systems is imperative to guarantee the dependability of the systems before they are being put to use. Moreover, it is beneficial to assess the SoC robustness in early design phase in order to significantly reduce the cost and time of re-design. To fill such needs, in this study, we propose a useful IP-based SoC-level risk model using failure mode and effects analysis (FMEA) method to assess the robustness of a SoC in SystemC transaction-level modeling (TLM) design level. The proposed risk model is able to facilitate the measure of the robustness and scales of failure-induced risks in a system, which can be used to identify the critical components and major failure modes for protection so as to effectively reduce the impact of failures to the system. A case study is used to demonstrate our risk model under CoWare Platform Architect environment. A system verification tool was created to assist us in measuring the robustness of the system, in locating the weaknesses of the system, and in understanding the effect of faults on system failure behavior during the SoC design phase. The contribution of this work is to promote the dependability verification to TLM abstraction level that can significantly enhance the simulation performance, and provide the comprehensive results to validate the system dependability in early design phase for safety-critical applications.
Industrial Embedded Systems, 2009. SIES '09. IEEE International Symposium on; 08/2009
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IEEE Fourth International Symposium on Industrial Embedded Systems - SIES 2009, Ecole Polytechnique Federale de Lausanne, Switzerland, July 8 - 10, 2009; 01/2009
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ABSTRACT: As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. In this study, we present a new approach of system-bus fault injection in SystemC design platform, which can be used to assist us in performing the FMEA procedure during the SoC design phase. We demonstrate the feasibility of the proposed fault injection mechanism with an experimental ARM-based system.
Secure System Integration and Reliability Improvement, 2008. SSIRI '08. Second International Conference on; 08/2008
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ABSTRACT: Embedded systems, and also the embedded microprocessors, have encountered the reliability challenge because the occurring probability of soft errors has a rising trend. When they are applied to safety-critical applications, designs with the fault tolerant consideration are required. For the complicated embedded systems or IP-based system-on-chip (SoC), it is unpractical and not cost-effective to protect the entire system or SoC. Analyzing the vulnerability of systems can help designers not only invest limited resource on the most crucial region but also understand the gain derived from the investment. In this paper we propose a model to fast estimate the microprocessor's vulnerability with only slight simulation effort. From our assessment results, the rank of component vulnerability related to the probability of causing the microprocessor failure can be acquired. By choosing one of the mainstream microprocessors - VLIW (Very Long Instruction Word) processor - as an example, the practical usefulness of our estimation model is demonstrated.
Secure System Integration and Reliability Improvement, 2008. SSIRI '08. Second International Conference on; 08/2008
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Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings; 01/2006
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Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, CDES 2006, Las Vegas, Nevada, USA, June 26-29, 2006; 01/2006
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ABSTRACT: In this paper, an effective fault-tolerant framework offering very high error coverage with zero detection latency is proposed to protect the data paths of VLIW processor cores. The feature of zero detection latency is essential to real-time error-recovery. The proposed framework provides the error-handling schemes of varying hardware complexity, performance and error coverage to be selected. A case study with an experimental VLIW architecture implemented in VHDL was used to demonstrate the impacts of our technique on hardware overhead and performance degradation. The fault injection experiments were performed to characterize the effects of fault-occurring frequency as well as workload variations on the error coverage, and the permanent faults on the length of time spent for error-recovery. The results observed from the experiments show that our approach can well protect the VLIW data paths even in a very severe fault scenario. As a result, the proposed fault-tolerant VLIW core is quite suitable for the highly dependable embedded applications.
Microprocessors and Microsystems.
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ABSTRACT: Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the coverage and latency. In this paper, a new, hybrid error-detection approach offering a very high coverage with zero detection latency is proposed to protect the data paths of high-performance microprocessors. The feature of zero detection latency is essential to real-time error recovery. The hybrid error-detection approach is to combine the duplication with comparison, triple modular redundancy (TMR) and self-checking mechanisms to construct a formal framework, which allows the error-detection schemes of varying hardware complexity, performance and error-detection coverage to be incorporated. An experimental 32-bit VLIW core was employed to demonstrate the concept of hybrid detection approach. The hardware implementations in VHDL and simulated fault injection experiments were conducted to measure the interesting design metrics, such as hardware overhead, performance degradation and error-detection coverage.
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ABSTRACT: As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. The system bus, such as AMBA AHB, provides an integrated platform for IP-based SoC. Apparently, the robustness of system bus plays an important role in the SoC reliability. In this study, we propose a useful bus system vulnerability model and present a thorough analysis of system bus vulnerability in SystemC transaction-level modeling (TLM) design level by injecting faults into the bus signals, which can assist us in predicting the robustness of the system bus, in locating the weaknesses of the bus system, and in understanding the effect of bus faults on system behavior during the SoC design phase. The impact of benchmarks on system bus vulnerability is also addressed. The contribution of this work is to promote the dependability verification to TLM abstraction level that can significantly enhance the simulation performance, and provide the comprehensive results to validate the system bus dependability in early design phase for safety-critical applications.
