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Byoung Hak Hong,
Young Chai Jung,
Jae Sung Rieh,
Sung Woo Hwang, Keun Hwi Cho,
K.H. Yeo,
S.D. Suk,
Y.Y. Yeoh,
M. Li,
Dong-Won Kim,
Donggun Park,
Kyung Seok Oh,
Won-Seong Lee
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ABSTRACT: Temperature-dependent electrical transport measurements of cylindrical shaped gate-all-around silicon nanowire p-channel MOSFET were performed. At 4.2 K, they show current oscillations, which can be analyzed by single hole tunneling originated from nanowire quantum dots. In addition to this single hole tunneling, one device exhibited strong current peaks, surviving even at room temperature. The separations between these current peaks corresponded to the energy of 25 and 26 meV. These values were consistent with the sum of the bound-state energy spacing and the charging energy of a single boron atom. The radius calculated from the obtained single-atom charging energy was also comparable to the light-hole Bohr radius.
IEEE Transactions on Nanotechnology 12/2009; · 2.29 Impact Factor
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Luryi Choi,
Byoung Hak Hong,
Young Chai Jung, Keun Hwi Cho,
Kyoung Hwan Yeo,
Dong-Won Kim,
Gyo Young Jin,
Kyung Seok Oh,
Won-Seong Lee,
Sang-Hun Song,
Jae Sung Rieh,
Dong Mok Whang,
Sung Woo Hwang
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ABSTRACT: The mobility-degradation factor and the series resistance of cylindrical gate-all-around silicon nanowire field-effect transistors are extracted using the same mobility-degradation model as in the case of planar MOSFETs. The extraction is done by defining an asymptotic voltage as a function of the saturation current measured from devices with various lengths. The extracted mobility-degradation factor is an order of magnitude larger than those of other planar MOSFETs. This result suggests that, while the all-around gate can turn off the electron channel effectively, it creates more interface scattering in the strong inversion condition. The extracted series resistance is mostly due to the crowding of the electron flow along the sidewall of the n+ contact region making an abrupt joint with the nanowire.
IEEE Electron Device Letters 07/2009; · 2.85 Impact Factor
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Luryi Choi,
Byoung Hak,
Young Chai Jung, Keun Hwi Cho,
Hwan Kyoung,
Dong-Won Yeo,
Gyo Young Kim,
Kyung Seok Jin,
Won-Seong Oh,
Sang-Hun Lee,
Jae Song,
Rieh Sung,
Dong Mok Whang,
Sung Woo Hwang
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ABSTRACT: The mobility-degradation factor and the series resis-tance of cylindrical gate-all-around silicon nanowire field-effect transistors are extracted using the same mobility-degradation model as in the case of planar MOSFETs. The extraction is done by defining an asymptotic voltage as a function of the satura-tion current measured from devices with various lengths. The extracted mobility-degradation factor is an order of magnitude larger than those of other planar MOSFETs. This result suggests that, while the all-around gate can turn off the electron channel effectively, it creates more interface scattering in the strong inver-sion condition. The extracted series resistance is mostly due to the crowding of the electron flow along the sidewall of the n+ contact region making an abrupt joint with the nanowire. Index Terms—Gate-all-around (GAA), mobility-degradation factor, nanowire, series resistance, silicon.
01/2009; 30.
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ABSTRACT: In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at off current of 1nA/mum for NMOS and PMOS, respectively.
SOI Conference, 2008. SOI. IEEE International; 11/2008
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ABSTRACT: We reported the fabrication and characterization of a new type of silicon-on-insulator (SOI) single-electron transistor utilizing usual CMOS sidewall gate structures. We used oxide sidewall spacer layers as well as two poly-Si finger gates on an SOI wire mesa as implantation masks, to form tunnel barriers and thus a quantum dot (QD) that is smaller than the spacing between polygates. Characterization results exhibited clear Coulomb oscillations persisting up to 30 K. The Coulomb energy and the size of the QD extracted from three devices were consistent with the spacing between two poly-Si gates of each device. Furthermore, the junction capacitance of each device was almost constant and only the gate capacitance varied. These analyses suggested that the size of the QD was fully controlled by the process.
IEEE Transactions on Nanotechnology 10/2008; · 2.29 Impact Factor
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Kyoung Hwan Yeo, Keun Hwi Cho,
Ming Li,
Sung Dae Suk,
Yun-young Yeoh,
Min-Sang Kim,
Hyunjun Bae,
Ji-Myoung Lee,
Suk-Kang Sung,
Jun Seo,
Bokkyoung Park,
Dong-Won Kim,
Donggun Park,
Won-Seoung Lee
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ABSTRACT: Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, V<sub>TH</sub> window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire width is, the faster program speed and the larger V<sub>TH</sub> shift are achieved. P/E operations in NAND string with GAA SONOS nanowire are demonstrated for the first time.
VLSI Technology, 2008 Symposium on; 07/2008
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Sung Dae Suk,
Kyoung Hwan Yeo, Keun Hwi Cho,
Ming Li,
Yun Young Yeoh,
Sung-Young Lee,
Sung Min Kim,
Eun Jung Yoon,
Min Sang Kim,
Chang Woo Oh,
Sung Hwan Kim,
Dong-Won Kim,
Donggun Park
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ABSTRACT: A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.
IEEE Transactions on Nanotechnology 04/2008; · 2.29 Impact Factor
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ABSTRACT: We developed titanium nitride (TiN) based nanoelectromechanical (NEM) switch with the smallest suspension air-gap thickness ever made to date by a “top-down” complementary metal-oxide semiconductor fabrication methods. Cantilever-type NEM switch with a 15-nm-thick suspension air gap and a 35-nm-thick TiN beam was successfully fabricated and characterized. The fabricated cantilever-type NEM switch showed an essentially zero off current, an abrupt switching with less than 3 mV/decade, and an on/off current ratio exceeding 105 in air ambient. Also achieved was an endurance of over several hundreds of switching cycles under dc and ac biases in air ambient.
Applied Physics Letters 03/2008; 92(10):103110-103110-3. · 3.84 Impact Factor
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Min-Sang Kim,
Weon Wi Jang,
Ji-Myoung Lee,
Sung-Min Kim,
Eun-Jung Yun, Keun-Hwi Cho,
Sung-Young Lee,
In-Hyuk Choi,
Jun-Bo Yoon Yong,
Dong-Won Kim,
Donggun Park
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ABSTRACT: As design rule is scaled down in complementary metal-oxide-semiconductor (CMOS) device, the several disadvantages based on electric field effect in CMOS device were emerged such as short channel effect, junction leakage and gate oxide leakage current (J.D. Meindl, 2001). Non-CMOS based device using micro/nanoelectromechanical systems (MEMS/NEMS) switch have been proposed as one of the alternatives (R.L. Badzey et al., 2004), (Abele et al., 2006), (W.W. Jang et al., 2007). Devices based on MEMS/NEMS switch show excellent on-off current characteristics due to an almost zero off current and abrupt on-off current transition. Also, they have robustness under harsh environments such as X-ray, radiation, and low/high temperature. In this work, two types of two terminal NEMS switch with the smallest dimensions ever made were proposed and fabricated. Moreover, their electrical characteristics were provided.
Semiconductor Device Research Symposium, 2007 International; 01/2008
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Sung Dae Suk,
Ming Li,
Yun Young Yeoh,
Kyoung Hwan Yeo, Keun Hwi Cho,
In Kyung Ku,
Hong Cho,
WonJun Jang,
Dong-Won Kim,
Donggun Park,
Won-Seong Lee
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ABSTRACT: Nanowire size (dNW) dependency of various electrical characteristics on gate all around twin silicon nanowire MOSFET (TSNWFET) is investigated to understand overall performance of nanowire transistor deeply. When dNW decreases, current drivability (Ion) normalized by circumference at the same VG-VTH improves and maximizes at dNW of 4 nm. And mobility is also estimated with capacitance and series resistance. All the experimental investigation shows that dNW of 4 nm is the best point to maximize the volume inversion effect on gate all around nanowire MOSFET.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: Strained silicon nanowire transistor with embedded SiGe (e-SG) source/drain is investigated for the first time on experiments. By compressive stress induced by e-SG, PMOS performance is improved by about 85%. <110>-oriented nanowire channel also contributes 80% PMOS performance improvement relative to <100> direction. By combination of uniaxial stress and <110> channel direction, up to 136% PMOS performance enhancement is obtained so that superior PMOSFET to NMOSFET is for the first time observed with silicon channel material.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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Keun Hwi Cho,
Sung Dae Suk,
Yun Young Yeoh,
Ming Li,
Kyoung Hwan Yeo,
Dong-Won Kim,
Donggun Park,
Won-Seong Lee,
Young Chai Jung,
Byung Hak Hong,
Sung Woo Hwang
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ABSTRACT: The characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with a radius of 5 nm have been measured in temperatures T ranging from 4 to 300 K. The dependence of the off-current suggests that thermal generation in the channel is the main leakage mechanism. The dependence of the subthreshold swing exhibits no body effects but shows degradations due to slight differences in the threshold voltages and in the body effect constants of the twin nanowires. The T dependence of the peak normalized transconductance g<sub>m</sub> /V<sub>DS</sub> gives a clue of 1-D phonon scattering and suggests that surface roughness scattering at the nanowire wall is dominant at low values.
IEEE Electron Device Letters 01/2008; · 2.85 Impact Factor
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Sung Dae Suk,
Kyoung Hwan Yeo, Keun Hwi Cho,
Ming Li,
Yun young Yeoh,
Ki-Ha Hong,
Sung-Han Kim,
Young-Ho Koh,
Sunggon Jung,
WonJun Jang,
Dong-Won Kim,
Donggun Park,
Byung-II Ryu
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ABSTRACT: We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mus at V<sub>d</sub> = 2 V, V<sub>g</sub> = 6 V and erase speed of 1 ms at V<sub>d</sub> = 4.5 V, V<sub>g</sub> = -6 V are achieved with 2~3 nm nanowire and 30 nm gate. Nanowire size below 10 nm dependencies on V<sub>th</sub> shift (DeltaV<sub>th</sub>) and the program/erase (P/E) characteristics are investigated. As nanowire diameter (d<sub>nw</sub>) decreases, faster program speed and larger DeltaV<sub>th</sub> are observed.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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Kyoung Hwan Yeo,
Sung Dae Suk,
Ming Li,
Yun-young Yeoh, Keun Hwi Cho,
Ki-Ha Hong,
SeongKyu Yun,
Mong Sup Lee,
Nammyun Cho,
Kwanheum Lee,
Duhyun Hwang,
Bokkyoung Park,
Dong-Won Kim,
Donggun Park,
Byung-Il Ryu
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ABSTRACT: GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/mum while n-TSNWFET shows on-current of 1.44 mA/mum. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3D and quantum simulation
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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ABSTRACT: the authors report transport experiments on gate-all-around (GAA) TSNWFETs fabricated by top-down CMOS processes. The nanowire with 45 nm gate length exhibits single electron tunneling, and the total capacitance extracted from the measured data is in good agreement with the self-capacitance of an ideal cylinder. The nanowire with 125 nm gate length shows conductance quantization suggesting ballistic transport. The temperature dependence of the conductance steps is consistent with the crossover from classical to ballistic
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
