Jongchan Kang

Pohang University of Science and Technology, Antō, North Gyeongsang, South Korea

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Publications (11)13.24 Total impact

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    ABSTRACT: A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-μm standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g<sub>m3</sub> and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P<sub>1dB</sub> with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P<sub>1dB</sub>. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.
    IEEE Journal of Solid-State Circuits 07/2006; · 3.06 Impact Factor
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    Jongchan Kang, Daekyu Yu, Youngoo Yang, Bumman Kim
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    ABSTRACT: The linearity of a 0.18-μm CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C<sub>gs</sub>), which is the dominant nonlinear source, and partially from drain junction capacitance (C<sub>jd</sub>). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-μm standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P<sub>out</sub>, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P<sub>1dB</sub>. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P<sub>out</sub>, 18.9 dB of power gain and 35% of PAE at P<sub>1dB</sub>. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.
    IEEE Journal of Solid-State Circuits 06/2006; · 3.06 Impact Factor
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    Jongchan Kang, A. Hajimiri, Bumman Kim
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    ABSTRACT: A single-chip linear CMOS PA for OFDM WLAN applications adopts a fully differential topology with transformer-type output matching and operates from a 3.3V supply. All of the components, including the input balun and output transformer, are integrated on a single 0.18mum CMOS die and no off-chip component is required
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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    ABSTRACT: A 2.4-GHz Doherty CMOS power amplifier (PA) with ultra-high efficiency [power added efficiency (PAE)] is presented. A 0.13-mum standard CMOS process is employed and the two-stage circuit is configured for a 3.2-V operation. For a compact realization of the circuit, all matching circuits including a quarter wave transformer and input phase compensation transmission lines are implemented with lumped components. To modulate properly and maximize the PAE at P1 dB, the input power of the class C peaking power cell is adjusted by optimizing the gate bias of the peaking driver cell. By doing so, the gain compression of the carrier cell is compensated by the gain expansion of the peaking cell up to the full power. This amplifier delivers a 22.7dBm of P1 dB and 60% of PAE with 25dB of power gain at 2.4 GHz. The PAE at 5 dB backed-off power level shows about 35%. The excellent PAE of the circuit is the best data ever reported from linear CMOS PAs. The successful demonstration of the Doherty CMOS PA with lumped components is expected to be applied for a full-integration of the circuit
    IEEE Microwave and Wireless Components Letters 01/2006; 16(9):505-507. · 1.78 Impact Factor
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    ABSTRACT: An improved large-signal model of RF LDMOS was developed to enhance the accuracy while maintain the physical meaning. Nonlinear drift resistance was carefully investigated and extracted directly from DC measurement data using the concept of the common intrinsic drain voltage in two or more LDMOSs with different LDD lengths. The intrinsic part of the LDMOS was constructed with the popular BSIM-based model. The model was validated in DC and RF results and had good agreement with measured data.
    Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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    ABSTRACT: We present a 2.45 GHz fully-differential CMOS power amplifier (PA) with high efficiency and linearity. We have adopted a 0.18 μm standard CMOS process with Cu-metal and all components of the 2-stage circuit are integrated into one chip. To improve the linearity, we adopt a new harmonic termination technique at the common source along with the normal harmonic termination at the drain. The harmonic termination at the source suppresses the second harmonic generated at the input C<sub>gs</sub>. The amplifier shows 17.5 dB of power gain and 20.5 dBm of P<sub>1dB</sub> with 37 % of PAE. Linearity measurements from a 2-tone test show that the power amplifier with the second harmonic termination at the source improves a maximum 6 dB of IMD3 and 7 dB of IMD5 over the amplifier with harmonic termination at the drain only. Furthermore, the linearity improvements appear over the entire range of the power level and the linearity remains low below 45 dBc of IMD3 and -57 dBc of IMD5 for an output power backed-off more than 5 dB from P<sub>1dB</sub>.
    Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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    ABSTRACT: We present a new large signal model of HBT for accurately fitting IC-VCE curves at the saturation region. Because of the highly doped base of HBT, the collector is high-level injected in the region. This model treats the high-level injected collector as an effective base width widening and the saturation current terms of Ebers-Moll model are modified accordingly. A new empirical function is used to describe the base width variation. The simulation results using the model follow the measured IC-VCE curves at the saturation region very well. For verification, this model is applied to a multi-finger HBT and load-pull simulation results based on the model are compared with measured ones.
    Microwave Conference, 2002. 32nd European; 10/2002
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    ABSTRACT: To accurately understand the linear characteristics of a heterojunction bipolar transistor (HBT), we developed an analytical nonlinear HBT model using Volterra-series analysis. The model considers four nonlinear components: r<sub>π</sub>, C<sub>diff</sub>, C<sub>depl</sub>, and g<sub>m</sub>. It shows that nonlinearities of r <sub>π</sub> and C<sub>diff</sub> are almost completely canceled by g <sub>m</sub> nonlinearity at all frequencies. The residual g<sub>m</sub> nonlinearity is highly degenerated by input circuit impedances. Therefore, r<sub>π</sub>, C<sub>diff</sub>, C<sub>depl</sub>, and g <sub>m</sub> nonlinearities generate less harmonics than C<sub>bc</sub> nonlinearity. If C<sub>bc</sub> is linearized, g<sub>m</sub> is the main nonlinear source of HBT, and C<sub>depl</sub> becomes very important at a high frequency. The degeneration resistor R<sub>E</sub> is more effective than R<sub>B</sub> for reducing g<sub>m</sub> nonlinearity. This analysis also shows the dependency of the third-order intermodulation (IM3) on the terminations of the source second harmonic impedances. The IM3 of HBT is significantly reduced by setting the second harmonic impedances of Z<sub>S</sub>,<sub>2ω2</sub> = 0 and Z<sub>S</sub>,<sub>ω2-ω1</sub> = 0
    IEEE Transactions on Microwave Theory and Techniques 08/2002; · 2.23 Impact Factor
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    ABSTRACT: A new collector undercut process using SiN protection sidewall has been developed for high speed InP/InGaAs single heterojunction bipolar transistors (HBTs). The HBTs fabricated using the technique have a larger base contact area, resulting in a smaller DC current gain and smaller base contact resistance than HBTs fabricated using a conventional undercut process while maintaining low C<sub>bc</sub>. Due to the reduced base contact resistance, the maximum oscillation frequency (f<sub>max</sub>) has been enhanced from 162 GHz to 208 GHz. This result clearly shows the effectiveness of this technique for high-speed HBT process, especially for the HBTs with a thick collector layer, and narrow base metal width
    IEEE Transactions on Electron Devices 07/2002; · 2.06 Impact Factor
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    ABSTRACT: A new layout for high-speed AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is presented. The layout is horseshoe shaped and designed to simultaneously reduce base resistance (R<sub>B</sub>) and base-collector capacitance (C<sub>BC</sub>). A horseshoe-shaped HBT and a conventional single-finger HBT with the same emitter width of 2 μm were fabricated and tested. The reduction of R<sub>B</sub> and C<sub>BC </sub> using the horseshoe-shaped HBT resulted in a 25% improvement of the maximum oscillation frequency (f<sub>max</sub>=130 GHz)
    Electronics Letters 10/2001; · 1.04 Impact Factor
  • Jongchan Kang, Bumman Kim
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    ABSTRACT: We present a 2.45 GHz CMOS power amplifier (PA) with high efficiency and linearity. A 0.18 µm standard CMOS process with low-loss Cu-metal is employed. With optimun design of the power cell for class AB operation, the PA delivers a 21.1 dBm of output power with 18.9 dB of power gain and 37 % of PAE at P 1dB . To effectively linearize the PA, a simple and area effective second harmonic tank is integrated on the chip and optimum biasing point is selected. Linearity measurements from 2-tone test show that IMD3 and IMD5 are maintained under -40 dBc and -50 dBc for an output power backed-off more than 5 dB from P 1dB . These results clearly show that CMOS PA is a fully compliant candidate with high speed data communication covering the OFDM systems.