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    ABSTRACT: A programmable radar signal processor architecture is described. It is designed to handle up to a 10-MHz analog/digital sample rate. The architecture consists of a front-end composed of a parallel array of programmable digital signal processing (DSP) devices, which performs the high-speed signal processing functions such as pulse compression, moving target indication, constant false alarm rate processing, etc., and outputs contact reports, to a back-end processor consisting of transputer microprocessors to perform post-detection processing. The processor is being developed to support the Point Defence Demonstration Radar
    Radar Conference, 1991., Proceedings of the 1991 IEEE National; 04/1991