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ABSTRACT: In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices.
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on; 01/2008
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ABSTRACT: This work presents a technique for the resource optimization of input multiplexed ROM-based Finite State Machines. This technique exploits the don't care value of the inputs to reduce the memory size as well as multiplexer complexity. This technique has been applied to a publicly available FSM benchmarks and implemented in a low-cost FPGA. Results have been compared with tools supported ROM and standard logic cells implementations. In a significant number of test cases, the proposed technique is the best design alternative, both in resource requirements and speed.
Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on; 07/2007
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ABSTRACT: A new approach for ROM implementation of finite state machines (FSM) is proposed, based on the selection of a subset of inputs in each state using multiplexers. This technique has been applied to different FSM standard benchmarks and very good results have been obtained.
Electronics Letters 10/2004; · 0.96 Impact Factor
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ABSTRACT: Address-event-representation (AER) is a communication protocol that emulates the nervous system's neurons communication, and that is typically used for transferring images between chips. It was originally developed for bio-inspired and real-time image processing systems. Such systems may consist of a complicated hierarchical structure with many chips that transmit images among them in real time, while performing some processing. In this paper several software methods for generating AER streams from images stored in a computer's memory are presented. A hardware version that works in real-time is also being studied. All of them have been evaluated and compared.
Emerging Technologies and Factory Automation, 2003. Proceedings. ETFA '03. IEEE Conference; 10/2003
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ABSTRACT: This paper addresses the problems arising in the calculation of numerical references (network function coefficients), essential for an appropriate error control in simplification before and during generation algorithms for symbolic analysis of large analog circuits. The conventional polynomial interpolation method reveals to be unable to handle the large circuit sizes needed, mainly due to the dramatic effect of round-off errors. This paper introduces a new algorithm able to accurately calculate the network function coefficients of large analog circuits in an efficient way
European Design and Test Conference, 1997. ED&TC 97. Proceedings; 04/1997
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ABSTRACT: SIRENA is a general simulation environment for artificial neural
networks, with emphasis towards CNNs. A special interest has been placed
in allowing the simulation and modelling of the non-ideal effects
expected from VLSI implementations. SIRENA allows the simulation of CNNs
in greater detail than conventional CNN simulators, and much more
efficiently than SPICE-type electrical simulators
Cellular Neural Networks and their Applications, 1994. CNNA-94., Proceedings of the Third IEEE International Workshop on; 01/1995
