-
Kwang-Jin Lee,
Beak-Hyung Cho,
Woo-Yeong Cho,
Sangbeom Kang,
Byung-Gil Choi,
Hyung-Rok Oh,
Chang-Soo Lee,
Hye-Jin Kim,
Joon-Min Park,
Qi Wang, [......],
Chang-Han Choi,
Won-Ryul Chung,
Du-Eung Kim,
Yong-Jin Yoon,
Kwang-Suk Yu,
Gi-Tae Jeong, Hong-Sik Jeong,
Choong-Keun Kwak,
Chang-Hyun Kim,
Kinam Kim
[show abstract]
[hide abstract]
ABSTRACT: A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are proposed. The 512 Mb PRAM has achieved read throughput of 266 MB/s through the proposed schemes. The write throughput was 0.54 MB/s in internal x2 write mode, and increased to 4.64 MB/s with x16 accelerated write mode at 1.8 V supply.
IEEE Journal of Solid-State Circuits 02/2008; · 3.23 Impact Factor
-
Hyung-rok Oh,
Beak-hyung Cho,
Woo Yeong Cho,
Sangbeom Kang,
Byung-gil Choi,
Hye-jin Kim,
Ki-sung Kim,
Du-eung Kim,
Choong-keun Kwak,
Hyun-geun Byun,
Gi-tae Jeong, Hong-sik Jeong,
Kinam Kim
[show abstract]
[hide abstract]
ABSTRACT: The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-μm CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.
IEEE Journal of Solid-State Circuits 02/2006; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The array of synthetic antiferromagnetic magnetic tunnel junctions (MTJs) consisting of the TiN/PtMn (15 nm)/CoFe (1.5 nm)/Ru (0.8 nm)/CoFe (1.5 nm)/AlO (1.2 nm)/NiFe (t<sub>1</sub> nm)/Ru (0.8 nm)/NiFe (t<sub>2</sub> nm)/Ta (10 nm)/TiN structure was fabricated into submicrometer dimensions. Magnetization switching field and magnetic domain structure were investigated by micromagnetic modeling as well as remanent magnetoresistive measurement. Domain structure was investigated to understand switching characteristics. The switching field depends on the thicknesses difference of two magnetic layers consisting of SAF free layer structure. When the thickness difference became 1.5 nm, the switching field was reduced to around 20 Oe with improved squareness.
IEEE Transactions on Magnetics 11/2005; · 1.36 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: As mobile appliances are prevailing in our daily lives, the nonvolatile memory suitable for mobile applications becomes indispensable elements and it is anticipated that the nonvolatile memory usage is much increased in future due to much diversified applications. Therefore it is very appropriate and important to look into where the nonvolatile memory technologies are now, what the challenges are, and where the future technologies should go. In this study, two major devices of nonvolatile memory i.e., NAND flash and NOR flash are reviewed and then the newly emerging nonvolatile memory i.e., PRAM (phase change memory), and FRAM (ferroelectric memory) are discussed.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
-
Hongil Yoon,
Jae Yoon Sim,
Hyun Suk Lee,
Kyu Nam Lim,
Jae Young Lee,
Nam Jong Kim,
Keum Yong Kim,
Sang Man Byun,
Won Suk Yang,
Chang Hyun Choi, Hong Sik Jeong,
Jel Hwan Yoo,
Dong Il Seo,
Kinam Kim,
Byung Il Ryu,
Chang Gyu Hwang
[show abstract]
[hide abstract]
ABSTRACT: Summary form only given. A 1.8 V 4 Gb DDR SDRAM for low voltage
and high speed at full density has reduced inter-bitline coupling noise
in the twisted open bit line architecture. Amplifier sensitivity and
sensing margin are improved by gain-controlled pre-sensing and active
calibration of the bitline reference voltage. For noise-immune
power-stabilized operation, three circuit schemes suitable for the SDRAM
are presented: (i) twisted open bitline (TOB) architecture; (ii)
gain-controlled pre-sensing (GCP); and (iii) reference bitline
calibration (RBC). The TOB scheme eliminates the coupling noise between
adjacent BLs by holding neighboring bitlines stable at the reference
voltage with the open readout and sensing using a reference BL from the
adjacent block. The GCP scheme increases the sensing margin and speed by
employing transconductance-matched pre-amplification. The RBC scheme
actively mimics the cell data retention characteristics and yields an
optimal voltage level for the reference BL from the charge-shared
voltage from replica BL pairs. Together with a chip-size-efficient core
signal repeating architecture, these schemes ensure reliable low-voltage
and high-speed cell and core operation
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International; 02/2001
-
Won Suk Yang,
Yeong Kwan Kim,
Soo Ho Shin,
Won Seok Lee,
Kyu Hyun Lee, Hong Sik Jeong,
Jong Ho Lee,
Tae Young Chung,
Heung Soo Park,
Sang In Lee,
Kinam Kim,
Moon Yong Lee,
Chang Gyu Hwang
[show abstract]
[hide abstract]
ABSTRACT: A novel integration technology with capacitor over metal (COM) for
0.15 μm stand-alone and embedded DRAMs is developed using a
self-aligned dual damascene (SADD) process, which offers great
breakthroughs. First, many back-end metallization issues encountered in
conventional COB (capacitor over bit line) DRAMs are simply overcome
because the capacitor is formed after the metal lines. Secondly, memory
cell capacitors can be integrated much more simply and easily compared
to those of conventional COB technology because the memory cell contact
and storage node are formed simultaneously. Furthermore, transistor
performance can be greatly improved because a novel poly-Si/Al<sub>2
</sub>O<sub>3</sub>/poly-Si capacitor is integrated at temperatures
below 400°C
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
-
Hongil Yoon,
Gi Won Cha,
Chang Sik Yoo,
Nam Jong Kim,
Keum Yong Kim,
Chang Ho Lee,
Kyu Nam Lim,
Kyu Chan Lee,
Jun Young Jeon,
Tae Sung Jung, Hong Sik Jeong,
Tae Young Jeong,
Ki Nam Kim,
Soo In Cho
[show abstract]
[hide abstract]
ABSTRACT: While on-chip data flight times approach a few tens of nanoseconds
for gigabit-scale DRAMs, a bandwidth over 250 MHz requires data input
and output timing accuracy within 0.3 ns. Although a high-speed data
interface can be achieved using precise clock generators such as delay
locked loop (DLL), skews due to a long data access path may cause loss
of internal timing margins. Diminished timing margin may be detrimental
to wave pipelining for high-bandwidth. This 1 Gb double data rate (DDR)
SDRAM featuring ODIC chip with nonODIC package (OCNOP),
cycle-time-adaptive wave pipelining (CTAWP), and variable stage analog
DLL achieves high performance despite stringent processing variations in
0.14 μm design rules
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International; 02/1999
-
[show abstract]
[hide abstract]
ABSTRACT: A new DRAM cell scheme using merged process with storage node and
memory cell contact called BC is introduced for free alignment tolerance
between memory cell contact and storage node. The new cell scheme and
conventional COB stacked cell scheme are compared for the misalignment
tolerance and photo and etch process issues. The new cell scheme is
processed in 0.15 μm minimum feature size and its results are
described including vertical SEM pictures, capacitance-voltage data, and
leakage current. This new cell scheme achieved the requirement of memory
cell capacitance of 25 fF/cell in 0.30 μm pitched 4 Gb DRAMs
Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International; 01/1999
