Hong Yu Yu

National University of Singapore, Singapore, Singapore

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Publications (16)37.43 Total impact

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    ABSTRACT: In this letter, new endurance degradation behaviors in the bipolar resistive random access memory devices with multilayered HfOx/TiOx are reported for the first time, showing almost a constant resistance in low resistance state and a gradually reduced resistance in high resistance state (HRS). Further investigations into the dependence of HRSs degradation speed on switching voltage and temperature reveal that the degradation is attributed to the oxygen ion (O2-) loss effect during RESET process, which leads to the insufficient O2- supply for recombining the oxygen vacancies. Possible technical solutions are then proposed to improve the endurance performance.
    IEEE Electron Device Letters 01/2013; 34(10):1292-1294. · 2.79 Impact Factor
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    ABSTRACT: In this paper, the ambient doping effect on negative/positive bias temperature instability (NBTI/PBTI) of single layer graphene field effect transistors (FETs) is investigated. In ambient air, the ΔVth of NBTI is comparable with that of PBTI under the same stress voltage at room temperature. The ΔVth of NBTI appears insensitive to temperature, while the ΔVth of PBTI increases significantly with rising temperatures, due to the thermally activated charging of ambient doped defects at the graphene/SiO2 interface. This effect also results in an abnormal recovery of NBTI. In an ambient vacuum, the ΔVth is much less than that in ambient air. In addition, the ΔVth of both NBTI and PBTI decreases substantially for higher temperatures in the vacuum. The adsorbed molecules are mainly responsible for the ΔVth under BTI stress and the back-gated graphene FETs in the air.
    IEEE Transactions on Electron Devices 01/2013; 60(8):2682-2686. · 2.06 Impact Factor
  • IEEE Electron Device Letters 10/2012; 33(10):1402-1404. · 2.79 Impact Factor
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    ABSTRACT: Large-scale rationally designed periodic Si nanopillar (SiNP) arrays of varying diameters and heights have been fabricated by a top-down method. The impacts of the structural parameters (e.g., diameter/periodicity/height) on the reflectance and absorption of the SiNP array have been extensively studied, and the results are in agreement with our theoretical prediction of Li et al. Owing to the notably enhanced light absorption of the optimized SiNP array, a short-circuit current density J <sub>sc</sub> of 34.3 mA/cm<sup>2</sup> was obtained on an axial p-n SiNP array surface-textured solar cell, which is the highest to date among reported Si nanowire/SiNP-based solar cells. J <sub>sc</sub> is significantly boosted compared to that of the untextured solar cell (18.1 mA/cm<sup>2</sup>), which implies that the SiNP array is a promising texturing technology for thin-film photovoltaic application.
    IEEE Transactions on Electron Devices 10/2011; · 2.06 Impact Factor
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    ABSTRACT: In this Letter, the optical properties of randomly positioned silicon nanowire arrays are studied. The result shows that position randomization with a filling ratio larger than 36% renders better absorptance over a broadband ranging from 300 to 1130 nm compared to regular structures. The ultimate efficiency of a 48% filling ratio position randomized nanowire structure is 13.4% higher compared to the optimized regularly arranged nanowire structure with the same thickness. The absorptance enhancement of random structures is attributed to lowered reflectance, more supported resonant modes, and broadening of existing resonance.
    Optics Letters 05/2011; 36(10):1884-6. · 3.39 Impact Factor
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    ABSTRACT: In this paper, the optical properties of the silicon nano-cone-hole (NCH) structure array are studied. The ultimate efficiency of the optimized NCH array is enhanced by 23.11% compared to an optimized nanohole array of the same thickness. The absorptance enhancement of the NCH arrays is attributed to its lowered reflectance, more supported resonant modes, and enhanced mode interaction. The angular dependence of ultimate efficiency is also investigated.
    Optics Letters 05/2011; 36(9):1713-5. · 3.39 Impact Factor
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    ABSTRACT: Inkjet-printed In-Ga-Zn oxide (IGZO) thin-film transistors (TFTs) with bottom-gate bottom-contact device architecture are studied in this paper. The impact of the IGZO film thickness on the performance of TFTs is investigated. The threshold voltage, field-effect mobility, on and off drain current, and subthreshold swing are strongly affected by the thickness of the IGZO film. With the increase in film thickness, the threshold voltage shifted from positive to negative, which is related to the depletion layer formed by the oxygen absorbed on the surface. The field-effect mobility is affected by the film surface roughness, which is thickness dependent. Our results show that there is an optimum IGZO thickness, which ensures the best TFT electrical performance. The best result is from a 55-nm-thick IGZO TFT, which showed a field-effect mobility in the saturation region of 1.41 cm<sup>2</sup>/V·s, a threshold voltage of 1 V, a drain current on/off ratio of approximately 4.3 × 10<sup>7</sup>, a subthreshold swing of 384 mV/dec, and an off-current level lower than 1 pA.
    IEEE Transactions on Electron Devices 03/2011; · 2.06 Impact Factor
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    ABSTRACT: In this paper, laser annealing is used to produce metal (Ag) nanoparticles as etching catalyst on a silicon surface, which enables controllable fabrication of large-scale nanohole array surface texturing without using a mask. Semispherical Ag nanoparticles with variable size and distribution are achievable by manipulating the laser annealing parameters and metal film thickness, and the underlying physics is clarified. The nanoholes array in silicon can then be realized by selective etching of silicon under Ag pattern. The optical characteristics suggest that the surface reflection can be significantly suppressed owing to the nanohole texturing, which is promising for thin film photovoltaic applications.
    Journal of Applied Physics 08/2010; · 2.21 Impact Factor
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    ABSTRACT: In this letter, we present the fabrication and characteristics of a gate-all-around SONOS Flash memory using a vertical Si nanowire (SiNW), which is proposed to be the key building block to realize the 3-D multilevel memory technology for ultrahigh-density application. A highly scaled SiNW with a diameter down to 50 nm using CMOS-compatible technology was achieved. Using an unoptimized SONOS gate stack (with the thickness of SiO<sub>2</sub>/Si<sub>3</sub>N<sub>4</sub>/SiO<sub>2</sub> ~ 5/5/6 nm), the devices exhibit well-behaved memory characteristics, in terms of program/erase window, retention, and endurance properties.
    IEEE Electron Device Letters 09/2009; · 2.79 Impact Factor
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    ABSTRACT: Cap layers have been used to modulate the effective work function (EWF) for high- /metal-gate CMOS devices. We have investigated the impact of stacking cap layers on the EWF. Stacked cap layers consisting of two sequential cap layers, including, Al<sub>2</sub>O<sub>3</sub>, Dy<sub>2</sub>O<sub>3</sub>, Sc<sub>2</sub>O<sub>3</sub> and La<sub>2</sub>O<sub>3</sub>, were formed on HfSiON or SiON as host dielectrics. It is demonstrated that the EWF change due to the stacked cap layers corresponds to the sum of the EWF change from each single cap layer. Furthermore, no host dielectric dependence on the shifts is observed. This behavior is attributed to the complete intermixing of the stacked cap layers with the host dielectrics.
    IEEE Electron Device Letters 08/2008; · 2.79 Impact Factor
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    ABSTRACT: A lanthanum (La)-doped HfN is investigated as an n-type metal gate electrode on SiO<sub>2</sub> with tunable work function. The variation of La concentration in (HfinfinLa<sub>1-x</sub>)N<sub>y</sub> modulates the gate work function from 4.6 to 3.9 eV and remains stable after high-temperature annealing (900degC to 1000degC), which makes it suitable for n-channel MOSFET application. An ultrathin high-fc dielectric layer was formed at the metal/SiO<sub>2</sub> interface due to the (HfinfinLa<sub>1-x</sub>)N<sub>y</sub> and SiO<sub>2</sub> interaction during annealing. This causes a slight reduction in the effective oxide thickness and improves the tunneling current of the gate dielectric by two to three orders. We also report the tunability of TaN with Al doping, which is suitable for a p-type metal gate work function. Based on our results, several dual-gate integration processes by incorporating lanthanum or aluminum into a refractory metal nitride for CMOS technology are proposed.
    IEEE Transactions on Electron Devices 12/2007; · 2.06 Impact Factor
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    ABSTRACT: A pFET threshold-voltage ( Vt ) reduction of about 200 mV is demonstrated by inserting a thin Al<sub>2</sub>O<sub>3</sub> layer between the high-k dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiO<sub>prop</sub>capped with 9 Aring of thin Al<sub>2</sub>O<sub>3</sub>obtains a low long-channel V t of -0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm<sup>2</sup> /V ldr s at 0.8 MV/cm (92% of universal value), a negligible equivalent- oxide-thickness (EOT) increase of 0.1 Aring (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of -0.7 V. This indicates that thin Al<sub>2</sub>O<sub>3</sub>obtains caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al<sub>2</sub>O<sub>3</sub>-capped HfSiO<sub>prop</sub> is not favorable because it increases the Vt by 50-140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5-0.8 Aring and the Vt instability by 5-13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, high-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO<sub>2</sub> interface.
    IEEE Transactions on Electron Devices 11/2007; · 2.06 Impact Factor
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    ABSTRACT: Conduction band-edge effective work functions (phi<sub>m,eff </sub>) are demonstrated with TaC<sub>x</sub> and TiN by means of La<sub>2</sub>O<sub>3</sub> capping of HfSiO<sub>x</sub> in a gate-first process flow with CMOS-compatible thermal budget. With TaC<sub>x</sub>, a 10- Aring-thick La<sub>2</sub>O<sub>3</sub> cap results in a phi <sub>m,eff</sub> of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1-2 Aring) and unaffected electron mobility. With TiN, non-nitrided La<sub>2</sub>O<sub>3</sub> capping results in a smaller phi<sub>m,eff</sub> reduction at a larger EOT increase, while with post-cap nitridation, the TiN phi<sub>m,eff</sub> is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on La<sub>2</sub>O<sub>3 </sub> capped stacks
    IEEE Electron Device Letters 07/2007; · 2.79 Impact Factor
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    ABSTRACT: The impact on the metal gate effective work function (EWF) of As ion implantation through TiN/TaN/HfO2 gate stack was investigated. An As implantation at 20 KeV reduces the flat-band voltage (VFB) for TiN/TaN/HfO2 capacitors (or equivalently reduces the EWF) by a maximum of 600 mV at a dose of 5× 1015 cm-2. This VFB reduction is correlated to the As pile-up at the TaN-HfO2 interface, as evidenced by a secondary ion mass spectroscopy (SIMS) study. The As ion accumulation at the interface of the gate electrode-dielectric interface is suggested to induce an interface dipole, contributing to the observed phenomena.
    Japanese Journal of Applied Physics 01/2007; 46. · 1.07 Impact Factor
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    ABSTRACT: A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-κ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)∼50%) results in: 1) an increase of the effective work function by ∼ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V<sub>o</sub>)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V<sub>o</sub>-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.
    IEEE Transactions on Electron Devices 07/2006; · 2.06 Impact Factor
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    ABSTRACT: In this paper, we review our recent work on the dynamic bias-temperature instability (BTI) in metal-oxide-semiconductor field effect transistors (MOSFETs) with ultrathin SiO2 and high-K gate dielectrics, operating in a digital inverter circuit. Key findings are: (1) For p-MOSFETs with ultrathin SiO2 gate dielectrics, negative BTI (NBTI) is mainly due to the generation of interface traps. Under dynamic NBTI stress, the interface traps generated in the stressing phase are subsequently passivated in the passivation phase with a zero gate bias. As a result, p-MOSFET lifetime is significantly enhanced and the enhanced lifetime is frequency-independent up to 100 kHz. (2) For n- and p-MOSFETs with ultrathin HfO2 gate dielectrics, BTI is mainly caused by charge trapping in HfO2. Similar lifetime enhancements in both n- and p-MOSFETs are observed under dynamic BTI stress. However, in contrast to SiO2 devices, dynamic BTI in HfO2 is strongly frequency-dependent, i.e., a high frequency results in a slight device degradation and hence a long lifetime. A physical model that accounts for two-step trapping and detrapping in HfO2 is proposed to explain frequency-dependent BTI in HfO2 gate dielectrics. Simulation results based on the new model shows excellent agreement with all experimental data.
    Japanese Journal of Applied Physics 01/2004; 43:7807-7814. · 1.07 Impact Factor