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ABSTRACT: Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (V<sub>Th</sub>) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric V<sub>Th</sub>, low T<sub>inv</sub> (~1.4 nm), and high I<sub>on</sub> (~780 ¿A/¿m) for N/PMOS without any intentional strain enhancement.
IEEE Transactions on Electron Devices 04/2010; · 2.32 Impact Factor
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IEEE Transactions on Electron Devices 01/2010; 57(3):626-631. · 2.32 Impact Factor
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H. Adhikari, H.R. Harris,
C.E. Smith,
Ji-Woon Yang,
B. Coss,
S. Parthasarathy,
Bich-Yen Nguyen,
P. Patruno,
T. Krishnamohan,
I. Cayrefourcq,
P. Majhi,
R. Jammy
[show abstract]
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ABSTRACT: Omega gate type pFETs with SiGe shell-Si core are demonstrated that show 30% mobility enhancement for (110) oriented fins and 46% mobility enhancement for (100) oriented fins compared to Si omega gate devices. Performance improvement is demonstrated because of higher mobility and inherent epitaxial strain, while the external resistance in the two SiGe and Si omega FETs is comparable. Performance can further be improved by uniaxial compressive stress.
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on; 05/2009
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J. Huang,
P.D. Kirsch,
Jungwoo Oh,
Se Hoon Lee,
P. Majhi, H.R. Harris,
D.C. Gilmer,
G. Bersuker,
Dawei Heh,
Chang Seo Park,
C. Park,
Hsing-Huang Tseng,
R. Jammy
[show abstract]
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ABSTRACT: This letter addresses mechanisms responsible for a high gate leakage current ( Jg ) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high- k /metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiO x interface layer. A secondary mechanism, i.e., Ge diffusion (ges3%) into high- k , results in high Jg . In the framework of this understanding, we optimized a high- k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ~ 0.9 nm with J <sub>g</sub> comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.
IEEE Electron Device Letters 04/2009; · 2.85 Impact Factor
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ABSTRACT: A new hot-carrier injection mechanism that depends on gate bias and body thickness in nanoscale floating-body MOSFETs has been identified using 2-D device simulation and hot-carrier degradation measurements. When gate voltage is sufficiently high and the body thickness is thin, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension (SE), resulting in impact ionization at the SE. Hot-carrier stress with accelerated gate voltage may lead to a huge overestimation of lifetime in nanoscale floating-body MOSFETs.
IEEE Electron Device Letters 02/2009; · 2.85 Impact Factor
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J. Huang,
P.D. Kirsch,
D. Heh,
C.Y. Kang,
G. Bersuker,
M. Hussain,
P. Majhi,
P. Sivasubramani,
D.C. Gilmer,
N. Goel,
M.A. Quevedo-Lopez,
C. Young,
C.S. Park,
C. Park,
P.Y. Hung,
J. Price, H.R. Harris,
B.H. Lee,
H.-H. Tseng,
R. Jammy
[show abstract]
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ABSTRACT: For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V<sub>t</sub>, as well as strongly affects mobility, N<sub>it</sub> and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V<sub>t</sub> tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO<sub>2</sub>) IL. T<sub>inv</sub>=1.15 nm and V<sub>t,lin</sub>=0.31 V was obtained while achieving the following attributes: mobility~70%, N<sub>it</sub> <5times10<sup>10</sup> cm<sup>-2</sup>, DeltaV<sub>t</sub><30 m V within wafer, BTI DeltaV<sub>t</sub> <40 m V at 125degC. By optimizing these gate stack factors, we have developed and demonstrated structures for 22 nm node LOP application.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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P D Kirsch,
P Sivasubramani,
J Huang,
CD Young,
CS Park,
K Freeman,
MM Hussain,
G Bersuker, H R Harris,
P Majhi,
others
ECS Transactions. 01/2009; 19(1):269-276.
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S H Lee,
P. Majhi,
J Oh,
B. Sassman,
C Young,
A. Bowonder,
W.Y. Loh,
K.J. Choi,
B.J. Cho,
H D Lee,
P. Kirsch, H.R. Harris,
W. Tsai,
S. Datta,
H.-H. Tseng,
S.K. Banerjee,
R. Jammy
[show abstract]
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ABSTRACT: High-performance sub-60 nm Si/SiGe (Ge: $sim$ 75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high- $kappa$ /metal gate stacks with $sim$ 1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length $(L_{g})$ devices demonstrate not only controlled short channel effects, but also an excellent on–off current $(I_{rm on}/I_{rm off})$ ratio $(simhbox{5} times hbox{10}^{4} hbox{at} hbox{55} hbox{-}hbox{nm} L_{g})$ . The intrinsic gate delay of these heterostructures is $sim$ 3 ps at $I_{rm on}/I_{ rm off}simhbox{10}^{4}$ . OFF -state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short $L_{g}$ devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.
IEEE Electron Device Letters 10/2008; 29(9):1017-1020. · 2.85 Impact Factor
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S. Suthram,
Y. Sun,
P. Majhi,
I. Ok,
H. Kim, H.R. Harris,
N. Goel,
S. Parthasarathy,
A. Koehler,
T. Acosta,
T. Nishida,
H-H. Tseng,
W. Tsai,
J. Lee,
R. Jammy,
S.E. Thompson
[show abstract]
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ABSTRACT: For the first time strain additivity on III-V using prototypical (100) GaAs n- and p-MOSFETs is studied via wafer bending experiments and piezoresistance coefficients are extracted and compared with those for Si and Ge MOSFETs. Further understanding of these results is obtained by using multi-valley conduction band model for n-MOS and performing k.p simulations for p-MOS. For GaAs n-MOSFET, uniaxial tensile stress is shown to enhance performance only for small stresses biaxial tensile stress is shown to be more beneficial. Importantly uniaxial compressive stress is beneficial for GaAs pMOSFETs and the piezoresistance effect is much larger than that seen for Si MOSFETs along the <110> channel direction. This works shows that intrinsic mobility and stress induced mobility enhancement are key knobs for scaling of III-V CMOSFETs.
VLSI Technology, 2008 Symposium on; 07/2008
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J. Huang,
P.D. Kirsch,
J. Oh,
S.H. Lee,
J. Price,
P. Majhi, H.R. Harris,
D.C. Gilmer,
D.Q. Kelly,
P. Sivasubramani, [......],
Y.N. Tan,
N. Goel,
C. Park,
P.Y. Hung,
P. Lysaght,
K.J. Choi,
B.J. Cho,
H-H. Tseng,
B.H. Lee,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiO<sub>x</sub> interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91 nm directly on SiGe with leakage equivalent to bulk Si. High I<sub>on</sub> (1.5times Si), and low subthreshold slope (73 mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.
VLSI Technology, 2008 Symposium on; 07/2008
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W.-Y. Loh,
P. Majhi,
S.-H. Lee,
J.-W. Oh,
B. Sassman,
C. Young,
G. Bersuker,
B.-J. Cho,
C.-S. Park,
C.-Y. Kang,
P. Kirsch,
B.-H. Lee, H.R. Harris,
H.-H. Tseng,
R. Jammy
[show abstract]
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ABSTRACT: We report on new observations of hot carrier (HC) degradation in strained Si/Si<sub>1-x</sub>Ge<sub>x</sub>(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction band under channel hot carrier stressing and uniform interface trap under drain avalanche hot carrier stressing, both of which can be mitigated by increasing Ge% in the Si/SiGe channel. Detailed study on Si capping layer (les 20 Aring) shows good immunity against Drain Avalanche Hot Carrier but is degraded under Channel Hot Carrier stressing. The results suggest that higher Ge% and thinner Si cap is preferably for hot carrier reliability for low voltage application with 10 yrs lifetime at operating voltage of -0.85 V.
VLSI Technology, 2008 Symposium on; 07/2008
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ABSTRACT: Longitudinal piezoresistance (pi) coefficients for n- and p-type double-gate (DG) FinFETs with sidewall channels along (110) surface and (110) channel direction are measured via wafer-bending experiments (51.4 and -37 X 10 <sup>-11</sup> Pa<sup>-1</sup> for n- and p-FinFETs, respectively) and are found to differ from bulk Si (110) (31.2 and -71.8 X 10 <sup>-11</sup> Pa<sup>-1</sup> for n- and p-Si, respectively). Compressive and tensile contact-etch-stop liners (CESLs) are fabricated on DG FinFETs and are found to induce higher channel stress than in planar MOSFETs, with 30% enhancement in the saturation current for the shortest channel-length devices in both n- and p-MOSFETs, whereas the long devices show little or no enhancement. The channel-length dependence of the enhancement suggests that stress coupling into the FinFET channels from the CESL occurs via the fin extensions and not through the gate.
IEEE Electron Device Letters 06/2008; · 2.85 Impact Factor
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[show abstract]
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ABSTRACT: Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate- source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps make finFETs a more attractive option for 32 nm technology node and beyond.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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J Huang,
P.D. Kirsch,
M. Hussain,
D. Heh,
P. Sivasubramani,
C Young,
D.C. Gilmer,
C S Park,
Y.N. Tan,
C Park, H.R. Harris,
P. Majhi,
G. Bersuker,
B H Lee,
H.-H. Tseng,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: We demonstrate for the first time a gate first high-k/metal gate (MG) nFET with EOT = 0.74 nm (T<sub>inv</sub> = 1.15 nm), low V<sub>t</sub> = 0.30 V, high performance [I<sub>on</sub>/I<sub>Off</sub> = 1310(muA/um) at 100(nA/um)], low leakage (> 200x reduction vs. SiO<sub>2</sub>/PolySi) and good PBTI. Low-k interface layer scaling and high-k La-doping enable this desirable EOT and V<sub>t</sub>. SiON/HfLaSiON can give similar interface quality as SiO<sub>2</sub>/HfSiON. Device performance was further improved 5% by strain engineering.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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S. Suthram, H.R. Harris,
M.M. Hussain,
C. Smith,
C.D. Young,
J.-W. Yang,
K. Mathews,
K. Freeman,
P. Majhi,
H.H.-H. Tseng,
R. Jammy,
S.E. Thompson
[show abstract]
[hide abstract]
ABSTRACT: Strain induced drive current enhancement on double-gate (DG) FinFETs from contact etch stop liners (CESLs) is modeled by performing wafer bending experiments. Longitudinal piezoresistance co-efficients for DG - FinFETs are extracted and shown to be different from the bulk Si values. This understanding is further used to gain insight into strain effects on FinFET ring-oscillator (RO) delay performance. FinFET hot- carrier degradation is observed to be enhanced for both tension and compression, and is explained to be due to increased impact- ionization from strain induced bandgap narrowing at the drain- body junction.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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S. Suthram,
P. Majhi,
G. Sun,
P. Kalra, H.R. Harris,
K.J. Choi,
D. Heh,
J. Oh,
D. Kelly,
R. Choi,
B.J. Cho,
M.M. Hussain,
C. Smith,
S. Banerjee,
W. Tsai,
S.E. Thompson,
H.H. Tseng,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: We demonstrate for the first time that both SiGe and Ge channel with high-k/metal gate stack pMOSFETs show similar uniaxial stress enhanced drive current as Si which is expected from k.p calculations. We also demonstrate experimentally that pMOSFETs with strained quantum wells (QW) in the Si-Ge system exhibited high performance and low off-state leakage comparable to optimized gate stacks on Si. These results significantly hasten the feasibility of realizing SiGe or Ge channel pMOSFETs for 22 nm and beyond.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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H.R. Harris,
S.E. Thompson,
S. Krishnan,
P. Kirsch,
P. Majhi,
C.E. Smith,
M.M. Hussain,
G. Sun,
H. Adhikari,
S. Suthram,
B.H. Lee,
H.-H. Tseng,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: We examine and demonstrate the benefit of high k and metal gate on Si(110) orientation-only CMOS devices and demonstrate not only good PMOS but competitive NMOS device performance. It is shown that high k / metal gates on NMOS Si(110) surface have higher than expected performance due to velocity saturation of minority carriers. Improvement in source/drain extension results in nearly symmetric CMOS output characteristics with no stress enhancement. Examining potential circuit impact reveals that the Si(110) surface provides a significant improvement in performance for UP and LSTP without large process complexity associated with mixed orientation CMOS approaches.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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P. D. Kirsch,
P. Sivasubramani,
J. Huang,
C. D. Young,
M. a. Quevedo-Lopez,
H. C. Wen,
H.N. Alshareef,
K. Choi,
C. S. Park,
K. Freeman, [......],
P. Majhi,
R. Choi,
P. Lysaght,
B.-H. Lee,
H.-H. Tseng,
R. Jammy,
T. S. Böscke,
D. J. Lichtenwalner,
J. S. Jur,
a. I. Kingon
Applied Physics Letters 01/2008; 92(9):092901. · 3.84 Impact Factor
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P. Sivasubramani,
T.S. Boscke,
J. Huang,
C.D. Young,
P.D. Kirsch,
S.A. Krishnan,
M.A. Quevedo-Lopez,
S. Govindarajan,
B.S. Ju, H.R. Harris,
D.J. Lichtenwalner,
J.S. Jur,
A.I. Kingon,
J. Kim,
B.E. Gnade,
R.M. Wallace,
G. Bersuker,
B.H. Lee,
R. Jammy
[show abstract]
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ABSTRACT: A dipole moment model explaining Vt tuning in HfSiON gated nFETs is proposed and its impact on performance and reliability is presented. La, Sc, Er, and Sr dopants are utilized due to their differing electronegativities and ionic radii. These dopants tune Vt in the range of 250-600 mV. V<sub>t</sub> tuning is found to be proportional to the net dipole moment associated with the Hf-O and rare earth (RE)-O bonds at the high-k/SiO<sub>2</sub> interface. The magnitude of this interfacial dipole moment is determined by the electronegativities and ionic radii of the RE cations. LaO<sub>x</sub> is the most effective dopant based on Vt, mobility, and reliability,
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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H.R. Harris,
P. Kalra,
P. Majhi,
M. Hussain,
D. Kelly,
Jungwoo Oh,
D. He,
C. Smith,
J. Barnett,
P.D. Kirsch,
G. Gebara,
J. Jur,
D. Lichtenwalner,
A. Lubow,
T.P. Ma,
Guangyu Sung,
S. Thompson,
Byoung Hun Lee,
Hsing-Huang Tseng,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La<sub>2</sub>O<sub>3</sub> capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
