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ABSTRACT: In this paper, we propose an analytic model for inverted-staggered organic thin-film transistors, and we use the proposed model to investigate the dependence of contact effect on the voltage bias, the film thickness of the organic semiconductor, and the channel length. In our model, the variable-range-hopping transport is adopted for the conduction in the horizontal direction to the semiconductor-insulator interface, and the space-charge-limited conduction is adopted for the conduction in the vertical direction by considering the molecular orientations. Qualitative agreement is obtained between simulation and measurement in the steady-state characteristics. From simulation study, we notice that the contact resistances vary with the source-gate voltage and with the source-drain voltage, the film thickness requires to be optimized to improve the on-current and the linearity in the linear operating regime, and the overlap length between the gate electrode and the source/drain contact needs to be guaranteed for the short-channel devices because it would not be scaled as much as the channel length.
IEEE Transactions on Electron Devices 06/2010; · 2.32 Impact Factor
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Seung Hyun Song,
Hyun-Sik Choi,
Rock-Hyun Baek, Gil-Bok Choi,
Min-Sang Park,
Kyung Taek Lee,
Hyun Chul Sagong,
Sang-Hyun Lee,
Sung Woo Jung,
Chang Yong Kang,
Yoon-Ha Jeong
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ABSTRACT: In this letter, a new physical 1/ f noise model is developed for double-stack high- k dielectric MOSFETs. This new model modifies the trapping-time-constant term in multistack unified noise model. Conventional 1/ f noise model is built on the simple square potential approximation which did not account the electric field dependence on trapping time constant. The new model takes into account of a resultant tunneling process from the actual sloped potential in order to eliminate the discrepancies of dielectric trap density on the dielectric thickness and the gate bias. Our model successfully predicts 1/ f noise data obtained from SiO<sub>2</sub>/HfO<sub>2</sub> double-stack high- k devices with various gate-dielectric thicknesses using a single set of modeling parameter.
IEEE Electron Device Letters 01/2010; · 2.85 Impact Factor
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Min Sang Park,
Kyong Taek Lee,
Seung Ho Hong,
Seung Hyun Song, Gil Bok Choi,
Rock Hyun Baek,
Hyun Sik Choi,
Hyun Chul Sagong,
Sung Woo Jung,
Chang Yong Kang,
B. Woo,
Yoon-Ha Jeong
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ABSTRACT: We present high pressure hydrogen annel (HPHA) effects in two types contact etch stop layer (CESL) nitride MOSFETs. Performances increased in both samples of using rapid thermal chemical vapor deposition (RTCVD) and plasma enhanced chemical vapor deposition (PECVD) nitride stress layers, but reliability only degraded in PECVD samples after HPHA.
Nanotechnology Materials and Devices Conference, 2009. NMDC '09. IEEE; 07/2009
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Hyun Chul Sagong,
Kyong Taek Lee,
Seung-Ho Hong,
Hyun-Sik Choi, Gil-Bok Choi,
Rock-Hyun Baek,
Seung-Hyun Song,
Min-Sang Park,
Jae Chul Kim,
Yoon-Ha Jeong,
Sung-Woo Jung,
Chang Yong Kang
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ABSTRACT: We investigate RF performances and hot carrier effects of nMOSFETs at cryogenic temperature. RF performances of HfO<sub>2</sub> dielectric nMOSFET at 77 K are improved more than those of SiO<sub>2</sub> dielectric nMOSFET although DC performances are improved similarly. The nMOSFET with HfO<sub>2</sub> dielectric has 127.4 GHz f<sub>T</sub> and 75.4 GHz f<sub>max</sub> at 77 K. In hot carrier injection measurement, g<sub>m</sub> of HfO<sub>2</sub> nMOSFET at 77 K is degraded more than 300 K although V<sub>th</sub> shift is less. The cause of g<sub>m</sub> reduction is discussed related to the trapping.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
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Jae Chul Kim,
Kyong Taek Lee,
Seung Hyun Song,
Min Sang Park,
Seung Ho Hong, Gil Bok Choi,
Hyun Sik Choi,
Rock Hyun Baek,
Hyun Chul Sagong,
Yoon-Ha Jeong,
Sung Woo Jung,
Chang Young Kang
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ABSTRACT: We have investigated reliability characteristics for a high-k/metal gate MOSFET with strain engineering under constant voltage stress (CVS). Using contact edge stop layer (CESL), tensile and compressive strains are applied to the channel region. Since the compressive MOSFET has more hydrogen in the CESL, the MOSFET has lower reliability characteristics than others. Though the hydrogen can passivate dangling bonds in the high-k dielectric, the passivated bonds are easily broken by voltage stress, which cause degradation of high-k layer.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
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ABSTRACT: A new extraction method of series resistance based on the radio frequency S-parameter measurement for sub -0.1 mum metal oxide semiconductor field-effect transistor is presented. The practical limit of conventional methods is analyzed from measurement and simulation. From this analysis, analytical expressions are derived, and linear regression techniques are used to extract the series resistances. The proposed method improves the accuracy and reduces the measurement frequency.
IEEE Microwave and Wireless Components Letters 11/2008; · 1.72 Impact Factor
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ABSTRACT: RF characteristics of a nanoscale MOSFET are measured and analyzed at temperatures ranging from 4.2 to 300 K for deep-space RF applications. This device shows a 197-GHz current gain cutoff frequency (f<sub>T</sub>) and a 162-GHz maximum oscillation frequency (f<sub>max</sub>) when operating at liquid-helium temperature, which represent a 60% and 80% improvement compared to room temperature performances, respectively, f<sub>T</sub> continually improves as the temperature decreases to near-liquid-helium temperature due to the decrease of gate capacitance (C<sub>gg</sub>). f<sub>max</sub> decreases as the temperature is lowered below 25 K due to the increase of gate resistance (R<sub>g</sub>).
IEEE Electron Device Letters 08/2008; · 2.85 Impact Factor
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ABSTRACT: An accurate extraction method for series resistance and capacitance based on RF S -parameter measurement in ultraleaky MOS devices is presented in this paper. The method is proven by using a three-element equivalent circuit model for a capacitor and a well-known microwave theory. The proposed method improves the measurement accuracy and significantly reduces the frequency-dependence of capacitance. This method is demonstrated for a 1.5 nm SiO<sub>2</sub> dielectric NMOSFET.
IEEE Electron Device Letters 04/2008; · 2.85 Impact Factor
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ABSTRACT: A new substrate network model for RF nano-CMOS and a parameter extraction method are proposed here. The model is composed of two resistances and one capacitance to accurately predict high frequency characteristics of nano-CMOS. The parameters are extracted and optimized both analytically and empirically using Z-parameter and Y-parameter analysis. A comparison between a conventional model and the proposed model shows that the proposed model is better in accuracy than conventional model. The measured and simulated data using the proposed model are in strong agreement up to 40.1 GHz
Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE; 11/2006
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Kyong Taek Lee,
Chang Yong Kang,
Hyun-Sik Choi,
Seung-Ho Hong, Gil-Bok Choi,
Jae Chul Kim,
Seung-Hyun Song,
Rock-Hyun Baek,
Min-Sang Park,
Hyun Chul Sagong,
Byoung Hun Lee,
Gennadi Bersuker,
Hsing-Huang Tseng,
Raj Jammy,
Yoon-Ha Jeong
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ABSTRACT: Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO2 thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < TIL and the traps of HfO2 in TIL < z < THK. The traps near the Si/SiO2 interface dominated the 1/f noise at higher frequencies, which is common in SiO2 dielectrics. For the HfO2/SiO2 gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO2 film than at the bottom of the interface.
Microelectronic Engineering 88(12):3411-3414. · 1.56 Impact Factor
