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ABSTRACT: Carrier trapping via tunneling into the gate oxide was implemented into a partial differential equation-based semiconductor device simulator to analyze the 1/f-like noise in silicon MOSFETs. Local noise sources are calculated using the carrier tunneling rates between trap centers in the oxide and those at the interface. Using the Green's transfer function approach, noise contributions from each node in the oxide mesh to the overall noise at the specified contact terminals are simulated. Unlike traditional 1/f noise analyses in MOSFETs, the simulator is capable of simulating noise for a wide range of bias voltages and device structures. The simulation results show that for an uniformly doped channel, the region in the oxide above the pinch-off point in saturation is most critical for low frequency noise generation while for a graded channel device the source side of the gate oxide region becomes important. By comparing the simulation results with the measured noise data, the oxide defect density in the noise producing regions can be profiled.
IEEE Transactions on Electron Devices 04/2003; · 2.32 Impact Factor
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ABSTRACT: Generation-recombination noise associated with bulk defect levels in silicon is modeled in a partial differential equation-based device simulator to study the maximum allowable defect density that guarantees generation-recombination (g-r) noise-free operation in the presence of hot-carrier effects and space-charge injection.
IEEE Transactions on Electron Devices 12/2002; · 2.32 Impact Factor
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ABSTRACT: The low-frequency 1/f-like noise of gated n<sup>+</sup>-p silicon
diodes has been measured and analyzed in terms of trapping and
detrapping of holes in defect centers located in the bulk section of the
space charge region at 0.43 eV below the conduction band. Both the trap
characteristics and their precise physical location are resolved from
the noise measurements showing that the noise producing defect region
moves closer to the metallurgical junction when forward bias is
increased. The noise measurements independently confirm that thermal
substrate pretreatments lower the defect density in the diodes
fabricated in Czochralski (CZ) grown substrates. The defect centers are
assumed to be associated with precipitated oxygen/dislocation complexes
IEEE Transactions on Electron Devices 01/1999; · 2.32 Impact Factor
