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ABSTRACT: A new fractional frequency divider is presented. It is based on a random dithering of the phase error. The divider output spectrum is cleaned from any fractional spurious tone. Moreover, as no noise shaping is applied, the proposed solution can be implemented in frequency synthesizers like Phase Locked Loops (PLL) without implication on the loop filter.
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on; 01/2011
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ABSTRACT: A voltage-controlled oscillator (VCO) with a central frequency of 56 GHz and a 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and by a 3-bit digital control bus using the same type of differential varactors. It achieves a record figure of merit, considering tuning range of 186.8 dBc/Hz and is able to address the full wireless high-definition multimedia interface band . The VCO is implemented in a 65-nm bulk CMOS process and dissipates 15 mW from a 1.2-V supply. Both fixed and parameterized electromagnetic models for inductors, interconnection structures, and transmission lines have been embedded in the classical design flow including layout verification and extraction, resulting in a very high level of simulation accuracy.
IEEE Transactions on Microwave Theory and Techniques 06/2010; · 1.85 Impact Factor
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ABSTRACT: A complete frequency synthesizer occupying 1.1 mm<sup>2</sup> in 65 nm CMOS is presented. It is composed of a push-push quadrature VCO that delivers two L0 signals in 20 and 40 GHz bands. The PLL consumes 80 mW including buffers, and achieves a phase noise lower than -100 and -97.5 dBc/Hz for the 20 GHz and the 40 GHz signals, respectively.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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ABSTRACT: This paper presents an overview of the available fractional-N frequency synthesizers dedicated to 60 GHz WPAN applications. The aim of this study is to determine the most suited architecture to fit the requirements of the upcoming 802.15.3 c standard.
Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on; 08/2009
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ABSTRACT: A voltage controlled oscillator (VCO) with 56 GHz central frequency and 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and a three-bit digital control bus using the same type of differential varactors. It achieves a record FOM<sub>T</sub> (considering tuning range) of 186.8 dBc/Hz and it is able to address the full wireless HDMI band. The VCO is implemented in a 65 nm bulk CMOS process and dissipates 15 mW from a 1.2 V supply.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
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ABSTRACT: On-chip test measures for new generation analog and mixed-signal RF circuits will replace performances that are becoming too costly or impossible to measure on-chip and/or on-tester. On one hand, these on-chip measurements must not degrade the DUT performances during the operation mode. On the other hand they must be highly correlated with the circuit performances. They should help to reduce test time and resources for production test while maintaining standard quality. For RF PLLs, the measurement of performances such as jitter, for example, is becoming unfeasible with increasing frequencies. This paper presents a DfT technique for RF PLLs using three built-in monitors that take measures highly correlated with device performances. A simple lock state test is required in a low cost digital tester. The built-in monitors are intended to give a Go/No-Go digital output. An evaluation of catastrophic fault coverage of the test technique is carried out on the VCO block through fault simulation. Parametric yield loss and defect level are evaluated using a statistical model of the VCO obtained by a Copulas-based probability density estimation technique. The case-study is a 65 nm CMOS RF PLL designed and manufactured at STMicroelectronics.
Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on; 05/2009
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ABSTRACT: In this paper, an 8 GHz 16<sup>th</sup> sub-harmonic injection-locked oscillator based on LC-oscillators and pulse generators is presented. It has been fully implemented in a VLSI 65 nm CMOS technology from STMicroelectronics and is dedicated to a double-loop frequency synthesizer. Under a nominal power supply of 1.2 V, the ILO core dissipates 20mA (without buffers) for a measured phase noise of -107 dBc/Hz at 100 kHz offset from the 8 GHz carrier. It also provides a synchronization bandwidth of 350 MHz, thanks to a double synchronization network.
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008
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ABSTRACT: This paper describes VCO designs based on varactor tuned Push-Push architecture. Two versions (powered under 1.2V and 1.8V) of the 79GHz oscillators have been designed in a 0.13mum SiGe BiCMOS technology, thus targeting automotive Radar and millimeter-wave applications. Their tuning ranges are respectively set on 6GHz (7.6%) and 7GHz (8.8%). The oscillator cores solely consume 18mW and 30mW, and both achieve low phase noise characteristics -102dBc/Hz at 1MHz offset from the carrier frequency (80GHz) and output powers of -18dBm and 0dBm respectively.
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on; 10/2008
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ABSTRACT: With devices operating at ever increasing speed, high resolution RF circuit performances are rapidly becoming non measurable even with the use of RF dedicated testers at affordable costs. This work deals with the development of BIST techniques for RF PLLs. Our aim is to find test measures that are highly correlated to performances that are too costly to measure on-chip and/or on-tester, in order to reduce test time and resources for production test while maintaining standard quality. A BIST output is typically a Go/No-Go output digital signal (most often associated with a structural test). In this work, we will consider as BIST outputs low frequency outputs from embedded monitors (BIST sensors) that can be used by the tester for the evaluation of circuit performances by means of regression functions (Alternate Test). In particular, we will consider monitoring the output of the phase frequency detector (PFD) for PLL BIST purposes. Our case-study is a 65 nm CMOS RF PLL designed and manufactured at ST Microelectronics.
Mixed-Signals, Sensors, and Systems Test Workshop, 2008. IMS3TW 2008. IEEE 14th International; 07/2008
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ABSTRACT: A high speed direct digital synthesizer (DDS) based transmitter architecture is presented. The DDS driven by a sigma delta (SigmaDelta) locks by injection an LC-tank oscillator on an upper harmonic. Moreover, the injection locked oscillator (ILO) provides a band-pass filtering within its locking range which rejects out of band SigmaDelta quantization noise. The DDS is detailed in order to explain how to design an output signal frequency close to the clock frequency. Then the architecture is modulated thanks to constant envelope modulation. Finally, ILO output is compared to high constraint mask such as GSM/DCS in order to simulate architecture capability.
Information, Communications & Signal Processing, 2007 6th International Conference on; 01/2008
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ABSTRACT: A SigmaDelta phase-interpolation direct digital synthesizer (DDS) is presented. This DDS generates frequencies from 400 MHz up to 500 MHz. Phase interpolation uses dual slope integration on a single capacitor and current is provided by a digital to analog converter (DAC). The SigmaDelta enables high frequency resolution and shapes quantization noise. The DDS has been integrated on a 65-nm CMOS STMicroclectronics technology. The power consumption is about 29 mVV without buffers under 1.2 V for a 500-MHz operating frequency.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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ABSTRACT: This paper describes a 5 GHz Analog Phase Interpolator (API) for clock synthesis and clock data recovery dedicated to multi-gigabit/s serial link applications. The system includes a 10 GHz LC Phase Locked Loop for clock generation and an Analog Phase Interpolator implemented with Current Mode Logic (CML) offering better phase noise and speed performances compared to CMOS logic. It has been implemented in ST's 65 nm RfCMOS technology. The core of the API occupies a silicon area of 0.09 x 0.17 mm2 and dissipates less than 22.56 mW from a 1.2 V voltage supply.
Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on; 10/2007
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ABSTRACT: This paper summarizes the electrical characterization of MIM capacitor realized in three dimensions. Manufacturing of the device is described, as well as an electrical comparison of three dielectrics, Si<sub>3</sub>N<sub>4</sub>, Al<sub>2</sub>O<sub>3</sub>, Ta<sub>2</sub>O<sub>5</sub> and two deposition methods, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Selecting Al<sub>2</sub>O<sub>3</sub> deposited by ALD, high density of 35 nF/mm<sup>2</sup> is obtained with low leakage current. Statistical measurements put forward the industrial robustness of the device integrated in BiCMOS technology. Three circuits embedding this new device are characterized: a high-pass filter, a voltage-controlled oscillator (VCO), and a phase-locked loop (PLL). They demonstrate excellent performances with significant area and assembly costs savings.
IEEE Journal of Solid-State Circuits 10/2007; · 3.23 Impact Factor
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ABSTRACT: This paper presents a novel burst generator architecture dedicated to Ultra Wideband wireless communication systems based on Impulse Radio techniques. Bursts are generated by using an oscillator output signal controlled both in magnitude and phase with a high-speed digital circuit in order to limit output signal bandwidth in accordance with IEEE 802.15.4a standard requirements. The design has been integrated on a single-chip in the 65nm CMOS STMicroelectronics technology under a 1.2 V supply voltage and functionnal measurements are presented.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
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ABSTRACT: This paper summarizes the electrical characterization of MIM capacitor realized in three-dimensional. High density of 35nF/mm<sup>2 </sup> is obtained with low leakage current. Its integration in BiCMOS technology is demonstrated and three circuits are characterized
Bipolar/BiCMOS Circuits and Technology Meeting, 2006; 11/2006
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ABSTRACT: In this paper a new concept of RF transmitter dedicated to low-power low-voltage applications using injection locked oscillator is described. A 2-GHz injection locked oscillator was implemented in a 0.35 mum BiCMOS STMicroelectronics technology in order to validate the theoretical results of the GMSK modulation of such oscillators
Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on; 10/2006
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ABSTRACT: In this paper a WCDMA/GSM/DCS/PCS multimode frequency synthesizer is presented. It consists in a double loop synthesizer with a programmable divider between each integer synthesizer in order to provide fractional steps. The synthesizer has been implemented in a STMicroelectronics 0.25 mum RF BiCMOS technology. Measured phase noise at 400 kHz of the 3.8 GHz carrier is -118 dBc/Hz. Power consumption is about 21 mA from a 2.5 V battery
Asian Solid-State Circuits Conference, 2005; 12/2005
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ABSTRACT: This paper presents theoretical results on phase modulation of injection locked oscillators. Experimental results on a 2-GHz fifth subharmonic injection locked oscillator (SBILO) integrated in a 0.35-μm BiCMOS STMicroelectronics technology are presented. Measured phase error added by the SBILO once locked by a GMSK modulated signal is negligible.
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European; 10/2005
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ABSTRACT: This paper presents a new PLL architecture that provides a larger frequency band of phase noise filtering in order to relax VCO building constraints. It consists in a classical PLL with a parallel band pass loop. This topology is called composite PLL. This paper presents some behavioral simulation of such PLL
Circuits and Systems, 2005. 48th Midwest Symposium on; 09/2005
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ABSTRACT: The paper presents a multiphase phase/frequency detector for a PLL-based frequency synthesizer that shares the phase correction information N times in the period of an RF step. The multiphase PFD provides a better rejection of reference spurious tone and reduces the charge pump current without bandwidth and loop filter modification. The 800 MHz MPFD PLL has been implemented in a STMicroelectronics BiCMOS 2.5 V 0.25 μm technology.
Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
