[Show abstract][Hide abstract] ABSTRACT: Metal contamination deposited on few-layer graphene (2-4 monolayers) grown on SiC(0001) was successfully removed from the surface, using low cost adhesive tape. More than 99% of deposited
silver contamination was removed from the surface via peeling, causing minimal damage to the
graphene. A small change in the adhesion of graphene to the SiC(0001) substrate was indicated by
changes observed in pleat defects on the surface; however, atomic resolution images show the
graphene lattice remains pristine. Thin layers of contamination deposited via an electron gun during
Auger electron spectroscopy/low energy electron diffraction measurements were also found to be
removable by this technique. This contamination showed similarities to “roughened” graphene
previously reported in the literature.
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 08/2015; 33(5):051802. DOI:10.1116/1.4928422 · 1.36 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Pleat defects in graphene grown on SiC(0001) were studied and used to determine the adhesion energy between few-layer graphene (3 ± 1 monolayers) and the substrate. An adhesion energy of 3.0 ± 1.0 1.6 J / m 2 was determined using a continuum model describing the buckling of the film and delamination. The continuum model used can be applied to any graphene-substrate system in which pleat formation occurs due to differences in thermal expansion. The large value of adhesion energy observed for graphene on SiC, compared with that on materials such as Ni, Cu, and SiO2, arises from delamination of the graphene film and buffer layer from the SiC substrate, which requires the breaking of covalent bonds. Preferential orientation of pleats at 120° with respect to each other was also observed; this is attributed to favorable formation of pleats along high symmetry directions of the graphene lattice.
[Show abstract][Hide abstract] ABSTRACT: Top-gated graphene field-effect transistors )GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27 nm thick Al2O3 gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100 degrees C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100 degrees C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100 degrees C. (C) 2014 AIP Publishing LLC.
[Show abstract][Hide abstract] ABSTRACT: Strained silicon is used to enhance performance in state-of-the-art CMOS. Under device operating conditions, the effect of strain is to reduce the carrier scattering at the channel by a smoother semiconductor surface. This has never been completely understood. This paper gives first evidence of the variation in surface roughness under realistic strained conditions. At the nanoscale, the SiO2/Si interface roughness is dependent on the scale of observation (self-affinity). To date, there is no experimental study of the SiO2/Si interface roughness scaling with strain. This work presents the effect of uniaxial and biaxial strains on the surface roughness of strained silicon-on-insulator films and wires using atomic force microscopy. Levels of strain ranging from 0% to 2.3%, encompassing those used in present CMOS devices have been investigated. It is shown that the silicon surface is affected by uniaxial and biaxial strains differently. Three surface roughness parameters have been analyzed: root mean square roughness, correlation length, and the Hurst exponent, which is used to describe the scaling behavior of a self-affine surface. The results show that the root mean square roughness decreases (up to ∼40%) with increasing tensile strain, whereas the correlation length increases (up to ∼63 nm/%) with increasing tensile strain. The Hurst exponent also varies with strain and with the undulation wavelength regime (between ∼0.8 and 0.2). This dependency explains why some models used to determine the carrier mobility from experiments fit the data better with a Gaussian form, whereas other models fit the data better with an exponential form.
[Show abstract][Hide abstract] ABSTRACT: This work presents experimental evidence of the formation mechanisms of few-layer graphene (FLG) films on SiC by nickel silicidation. FLG is formed by annealing of a 40 nm thick Ni layer on 6H-SiC at 1035ºC for 60 s, resulting in a Ni2Si layer which may be capped by any Ni that did not react during annealing. It has been proposed that FLG forms on top of the Ni during the high temperature stage. In contrast, during cooling, carbon atoms which were released during the silicidation reaction may diffuse back towards the Ni2Si/SiC interface to form a second FLG film. After annealing, layer-by-layer de-processing was carried out in order to unequivocally identify the FLG at each location using Atomic force microscopy (AFM) and Raman spectroscopy.
Materials Science Forum 02/2014; 778-780:1162-1165. DOI:10.4028/www.scientific.net/MSF.778-780.1162
[Show abstract][Hide abstract] ABSTRACT: Multilayer epitaxial graphene has been grown on the Si-face of 6H-SiC on-axis commercial substrates under high vacuum conditions and at growth temperatures up to 1900 °C, utilizing the standard sublimation growth technique and a modified SiC rapid thermal annealing system which allows for excellent control of heating and cooling ramp rates. The peak growth temperature and total growth time during the graphene growth step, along with the temperature of the initial substrate etch step, were all systematically varied in order to ascertain their effect on the formation of epitaxial graphene films on the SiC surface. Modifying the substrate etch temperature was found to have a significant impact on the morphology of the SiC substrate, with a uniform step structure only developing across the surface within a narrow temperature band. Furthermore, changing the values of the peak temperature or the growth time during the growth step were both shown to have a large effect on the resultant materials properties of the graphene films.
Materials Science Forum 02/2014; 778-780:1154-1157. DOI:10.4028/www.scientific.net/MSF.778-780.1154
[Show abstract][Hide abstract] ABSTRACT: Patterned few-layer graphene (FLG) films were obtained by local solid phase growth from nickel silicide supersaturated with carbon, following a fabrication scheme, which allows the formation of self-aligned ohmic contacts on FLG and is compatible with conventional SiC device processing methods. The process was realised by the deposition and patterning of thin Ni films on semi-insulating 6H-SiC wafers followed by annealing and the selective removal of the resulting nickel silicide by wet chemistry. Raman spectroscopy and X-ray photoelectron spectroscopy (XPS) were used to confirm both the formation and subsequent removal of nickel silicide. The impact of process parameters such as the thickness of the initial Ni layer, annealing temperature, and cooling rates on the FLG films was assessed by Raman spectroscopy, XPS, and atomic force microscopy. The thickness of the final FLG film estimated from the Raman spectra varied from 1 to 4 monolayers for initial Ni layers between 3 and 20 nm thick. Self-aligned contacts were formed on these patterned films by contact photolithography and wet etching of nickel silicide, which enabled the fabrication of test structures to measure the carrier concentration and mobility in the FLG films. A simple model of diffusion-driven solid phase chemical reaction was used to explain formation of the FLG film at the interface between nickel silicide and silicon carbide.
[Show abstract][Hide abstract] ABSTRACT: Few-layers graphene films (FLG) were grown by local solid phase epitaxy on a semi-insulating 6H-SiC substrate by annealing Ni films deposited on the Si and C-terminated faces of the SiC. The impact of the annealing process on the final quality of the FLG films is studied using Raman spectroscopy. X-ray photoelectron spectroscopy was used to verify the presence of graphene on the sample surface. We also demonstrate that further device fabrication steps such as dielectric deposition can be carried out without compromising the FLG films integrity.
Materials Science Forum 01/2013; 740-742:121-124. DOI:10.4028/www.scientific.net/MSF.740-742.121
[Show abstract][Hide abstract] ABSTRACT: Patterned Few Layers Graphene (FLG) films were grown by local solid phase epitaxy from nickel silicide supersaturated with carbon. The process was realised by annealing of thin Ni films deposited on the carbon-terminated surface of 6H-SiC semi-insulating wafer followed by wet processing to remove the resulting nickel silicide. Raman spectroscopy was used to investigate both the formation and subsequent removal of nickel silicide during processing. Characterisation of the resulting FLG films was carried out by Raman spectroscopy and Atomic Force Microscopy (AFM). The thickness of the final FLG film estimated from the Raman spectra varied from 1 to 3 monolayers for initial Ni layers varying from 3 to 20 nm thick. AFM observations revealed process-induced surface roughening in FLG films, however, electrical conductivity measurements by Transmission Line Model (TLM) structures confirmed that roughness does not compromise the film sheet resistance.
Materials Science Forum 05/2012; 717-720:629-632. DOI:10.4028/www.scientific.net/MSF.717-720.629
[Show abstract][Hide abstract] ABSTRACT: Nanomechanical testing of silicon is primarily motivated toward characterizing scale effects on the mechanical behavior. “Defect-free” nanoscale silicon additionally offers a road to large deformation permitting the investigation of transport characteristics and surface instabilities of a significantly perturbed atomic arrangement. The need for developing simple and generic characterization tools to deform free-standing silicon beams down to the nanometer scale, sufficiently equipped to investigate both the mechanical properties and the carrier transport under large strains, has been met in this research through the design of a versatile lab-on-chip. The original on-chip characterization technique has been applied to monocrystalline Si beams produced from Silicon-on-Insulator wafers. The Young’s modulus was observed to decrease from 160 GPa down to 108 GPa when varying the thickness from 200 down to 50 nm. The fracture strain increases when decreasing the volume of the test specimen to reach 5% in the smallest samples. Additionally, atomic force microscope-based characterizations reveal that the surface roughness decreases by a factor of 5 when deforming by 2% the Si specimen. Proof of concept transport measurements were also performed under deformation up till 3.5% on 40-nm-thick lightly p-doped silicon beams.
[Show abstract][Hide abstract] ABSTRACT: Surface roughness in uniaxially loaded strained Si has been studied experimentally using high-resolution atomic force microscopy and a microelectromechanical systems-based on-chip loading device. A reduction in rms roughness from 0.29 nm to 0.07 nm has been identified as strain increases from 0 to 2.8% (stress from 0 to 4.9 GPa). The correlation length of the roughness, also known to affect carrier mobility, increases with increasing strain up to 1.7% before reducing at larger levels of strain. These results partly explain the high-field mobility observed in strained Si, indicating that a modified correlation length should also be considered in transport modelling of strained Si.
[Show abstract][Hide abstract] ABSTRACT: The low frequency noise performance of strained Si heterojunction bipolar transistors (sSi HBTs) is presented for the first time. Conventional SiGe HBTs and Si bipolar junction transistors (BJTs), processed with strained Si devices, were also measured as a reference. It is found that a lower noise level is obtained in sSi HBTs for a given collector current, which is important for circuit applications, compared with either SiGe HBTs or Si BJTs. However, sSi HBTs exhibit greater low frequency noise compared with other devices at fixed base current. This is due to the presence of defects that are caused by the integration of the strain-relaxed buffer in the fabrication of sSi HBTs. The relationship between low frequency noise and defects is supported by material characterization.
IEEE Transactions on Electron Devices 12/2011; 58(12):4196-4203. DOI:10.1109/TED.2011.2167753 · 2.47 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Epitaxial growth of strained layers used for highspeed electronic devices can induce surface roughness, which impacts gate dielectric properties. To precisely understand the effect of roughness on the quality and reliability of dielectrics, high-spatial-resolution characterization techniques are required. In this paper, we use conductive atomic force microscopy (C-AFM) to enable gate leakage analysis at the nanoscale in fully processed high-mobility strained Si MOSFETs. This is achieved by the selective removal of the gate from the dielectric, followed by nanoscale C-AFM analysis of the dielectric surface. A Hertzian contact model has been used to account for the tip-sample contact area in order to extract the current density. The techniques are applied to strained Si and bulk Si devices with different surface morphologies and macroscopic electrical data. The results suggest that materials exhibiting long-scale surface undulations are prone to degraded dielectric properties because gate leakage is increased at the highly sloped regions of the roughness. This effect is masked during conventional macroscopic electrical measurements. The increasing leakage also leads to compromised dielectric reliability. Dielectric lifetime was assessed through device stressing and has been found to be related to the level of surface roughness induced by the underlying substrate.
IEEE Transactions on Electron Devices 12/2011; 58(11-58):4016 - 4023. DOI:10.1109/TED.2011.2164250 · 2.47 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This work addresses the paucity of roughness measurements by reporting on roughness parameters in uniaxial strained Si beams relevant for state of the art MOSFETs, nanowire and MEMS devices, with varying degrees of strain. Roughness is characterized by high resolution AFM and strain is characterized by Raman spectroscopy. Microstructures comprising a silicon nitride actuator are used to induce a wide range of stress levels in Si beams. The microstructures also allow the comparison of surface evolution in the strain direction (along the Si beam) compared with the unstrained direction (across the Si beam). A gradual reduction in rms roughness amplitude and increase in roughness correlation length in the direction of the applied stress are found for increasing values of strain. In contrast, surface roughness in the direction perpendicular to the applied stress remained largely unchanged from the unstrained initial state.
[Show abstract][Hide abstract] ABSTRACT: In this paper, a study of the noise performance of strained Si Heterojunction Bipolar Transistors (sSi HBTs) is presented. This novel device exhibits low noise levels compared with Si Bipolar Junction Transistors (Si BJTs) and SiGe Heterojunction Bipolar Transistors (SiGe HBTs) for the same collector current, which can lower the noise in circuit applications. This performance benefit originates from the high current gain in sSi HBTs. However, the latter shows a higher noise level compared with the other devices at fixed base current. This is due to the presence of defects that are caused by the integration of a strained relaxed buffer used in the fabrication of sSi HBTs. The relationship between low frequency noise and defects has also been demonstrated using material characterisation. I. INTRODUCTION
[Show abstract][Hide abstract] ABSTRACT: Strained Si and strained SiGe layers can increase the speed of MOS devices through enhanced electron and hole mobilities compared with bulk Si. However, epitaxial growth of strained Si and SiGe layers induces surface roughness which impacts gate dielectric properties including leakage, breakdown and interface traps. Gate dielectric quality is conventionally studied at a macroscopic level on individual transistors or capacitors. To understand precisely the effect of roughness on the quality and reliability of dielectrics on high mobility substrate devices requires high spatial resolution characterisation techniques. Device processing modifies the dielectric/semiconductor interface compared with its initial form. Therefore nanoscale analysis on completed devices is necessary. In this work, we present new techniques to enable gate leakage analysis on a nanoscale in fully processed high mobility MOSFETs. This is achieved by careful selective removal of the gate from the dielectric followed by C-AFM measurements on the dielectric surface. Raman spectroscopy, AFM and SEM (EDX) confirmed complete layer removal. The techniques are applied to strained Si devices which have different surface morphologies and different macroscopic electrical data. Dielectric reliability is also assessed through device stressing.
[Show abstract][Hide abstract] ABSTRACT: Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained Si<sub>0.7</sub>Ge<sub>0.3</sub> base on top of a relaxed Si<sub>0.85</sub>Ge<sub>0.15</sub> collector. By using a Si<sub>0.85</sub>Ge<sub>0.15</sub> virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain β of 27 × over a conventional silicon bipolar transistor and 11× over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level.
IEEE Transactions on Electron Devices 07/2010; 57(6-57):1243 - 1252. DOI:10.1109/TED.2010.2045667 · 2.47 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A variety of defects in the Si/SiGe system are known to have detrimental effects on the electrical performance of metal–oxide–semiconductor field-effect transistors with strained Si channels. The ability to characterize individual defect types is therefore key for the production of high quality material. In this work we examine defects in the strained Si/SiGe system using two etching techniques and atomic force microscopy (AFM). For the first time, wavelength filtering techniques were applied to AFM images to identify non-destructively surface steps associated with misfit dislocations (MDs). Quantification of dislocation density with this method was in good agreement with results obtained from the etching techniques. The material consisted of strained Si layers on thin strain-relaxed buffers (SRBs) grown by a carbon-induced relaxation technique. Using a single etch, threading dislocations (TDs) in the strained Si layer were observed separately from those in the SRB, while pit-defects which formed in strained Si following thermal annealing could be observed and distinguished from TDs. Using a different etching technique, stacking faults (SFs) formed in supercritical thickness strained Si layers were clearly distinguished from MDs at the Si/SiGe heterointerface, enabling the density of SFs in the strained Si to be evaluated. Together with the AFM image filtering, these procedures enable a comprehensive characterization of defects in the strained Si/SiGe system. The technique is suitable for high mobility epitaxial layers, employing high Ge contents, where partially relaxed supercritical thickness layers are often necessary.
Journal of Physics D Applied Physics 09/2009; 42(17). DOI:10.1088/0022-3727/42/17/175306 · 2.72 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.