D.R.W. Yost

Publications (6)2.32 Total impact

• Conference Proceeding: Characterization of a three-dimensional SOI integrated-circuit technology

  C.K. Chen, N. Checka, B.M. Tyrrell, C.L. Chen, P.W. Wyatt, D.R.W. Yost, J.M. Knecht, J.T. Kedzierski, C.L. Keast
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  ABSTRACT: This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
  SOI Conference, 2008. SOI. IEEE International; 11/2008
• Conference Proceeding: Scaling Three-Dimensional SOI Integrated-Circuit Technology

  C.K. Chen, K. Warner, D.R.W. Yost, J.M. Knecht, V. Suntharalingam, C.L. Chen, J.A. Burns, C.L. Keast
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  ABSTRACT: In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +/--0.5 mum wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a back-metal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.
  SOI Conference, 2007 IEEE International; 11/2007
• Article: A wafer-scale 3-D circuit integration technology

  J.A. Burns, B.F. Aull, C.K. Chen, Chang-Lee Chen, C.L. Keast, J.M. Knecht, V. Suntharalingam, K. Warner, P.W. Wyatt, D.-R.W. Yost
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  ABSTRACT: The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described
  IEEE Transactions on Electron Devices 11/2006; · 2.32 Impact Factor
• Conference Proceeding: 3D via etch development for 3D circuit integration in FDSOI

  J.M. Knecht, D.R.W. Yost, J.A. Burns, C.K. Chen, C.L. Keast, K. Warner
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  ABSTRACT: This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.
  SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
• Source

  Available from: fnal.gov

  Conference Proceeding: Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

  V. Suntharalingam, R. Berger, J.A. Burns, C.K. Chen, C.L. Keast, J.M. Knecht, R.D. Lambert, K.L. Newcomb, D.M. O'Mara, D.D. Rathman, D.C. Shaver, A.M. Soares, C.N. Stevenson, B.M. Tyrrell, K. Warner, B.D. Wheeler, D.-R.W. Yost, D.J. Young
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  ABSTRACT: A 1024×1024 integrated image sensor with 8 μm pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 μm×2 μm×7.5 μm 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm² and pixel responsivity of ∼9 μV/e at room temperature.
  Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005
• Conference Proceeding: Elimination of parasitic channels in fully depleted SOI CMOS

  C.K. Chen, C.L. Chen, P.W. Wyatt, P. Gouker, J.A. Burns, D.R.W. Yost, V. Suntharalingam, C.L. Keast
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  ABSTRACT: In this paper, we have identified and corrected two different mechanisms giving rise to low threshold parasitic channels and subthreshold shoulders in our FDSOI process. PMOS shoulders resulting from local gate penetration were eliminated by incorporating an edge implant and reducing BOX loss. These process modifications have significantly improved subthreshold behaviour of both n and pMOS devices and have substantially improved performance and yield of complex circuits.
  SOI Conference, 2003. IEEE International;