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ABSTRACT: This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices, revealing an important contribution of lateral charge migration at 150 °C, are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. Modeling results allow a detailed analysis of the retention transients of both planar and 3D SONOS arrays, evaluating, for the latter, the minimum dimensions needed to fulfill the retention requirements at 85 °C.
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European; 10/2011
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ABSTRACT: This paper presents a detailed investigation of the impact of cycling time and temperature on the threshold-voltage instability arising from damage recovery during data retention on nanoscale nand Flash. Statistical results from the programmed state show that instabilities result, on average, in a threshold-voltage loss, which increases logarithmically with the time elapsed since the end of cycling. The slope of the logarithmic behavior strongly depends on the electric field during data retention, the cycling dose, and the probability level at which the shift of the array cumulative distribution is monitored. Increasing the cycling time and temperature corresponds, instead, to an equivalent delay of the instant at which the first read operation on the array is performed. The delay is studied for a large variety of cycling and retention conditions, extracting the parameters required for a universal damage-recovery metric for nand.
IEEE Transactions on Electron Devices 09/2011; · 2.32 Impact Factor
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ABSTRACT: This paper presents a thorough investigation of the main variability effects in nanoscale nand Flash memories, considering their impact on device operation by means of a statistical compact model for the memory array. The compact model allows the accurate simulation not only of the nand string current in read conditions, including parasitic capacitive couplings among neighboring cells, but also of cell program and erase. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of both neutral and programmed cell threshold voltage is obtained for state-of-the-art and next-generation technology nodes. The good agreement between modeling and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on nand technology design.
IEEE Transactions on Electron Devices 09/2011; · 2.32 Impact Factor
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ABSTRACT: This paper investigates the statistical variability sources affecting the program operation of nanoscale charge-trap memories. Using the 3-D TCAD model presented in Part I of this work, featuring a Monte Carlo simulation approach to deal with discrete traps in the storage layer, atomistic doping in the substrate, and granular electron injection from the substrate to the storage layer, we consider the effect of three main variability sources impacting charge-trap memory programming: 1) the statistical process ruling electron injection and trapping; 2) the fluctuation in the number and position of the trapping sites; and 3) the statistical distribution of the threshold-voltage shift induced by stored electrons in presence of percolative substrate conduction. We show that the first variability source plays the dominant role in determining the statistical dispersion of cell threshold voltage during the program operation.
IEEE Transactions on Electron Devices 08/2011; · 2.32 Impact Factor
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ABSTRACT: This paper presents a detailed investigation of charge-trap memory programming by means of 3-D TCAD simulations accounting both for the discrete and localized nature of traps and for the statistical process ruling granular electron injection from the substrate into the storage layer. In addition, for a correct evaluation of the threshold-voltage dynamics, cell electrostatics and drain current are calculated in presence of atomistic doping, largely contributing to percolative substrate conduction. Results show that the low average programming efficiency commonly encountered in nanoscaled charge-trap memory devices mainly results from the low impact of locally stored electrons on cell threshold voltage in presence of fringing fields at the cell edges. Programming variability arising from the discreteness of charge and matter will be addressed in Part II of this paper.
IEEE Transactions on Electron Devices 08/2011; · 2.32 Impact Factor
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ABSTRACT: This letter investigates the impact of control-gate (CG) and floating-gate (FG) doping and geometry on the electron-injection spread (EIS) of nanoscale NAND Flash memories. Doping of CG polysilicon rules the reduction of the CG-to-FG capacitance when moving from the read to the program conditions, as a result of polysilicon depletion. The capacitance reduction is shown, however, to be nearly negligible for the EIS resulting from incremental step pulse programming, which, for the commonly adopted voltage steps, is mainly determined by the capacitance value in read conditions. Finally, the scaling trend of the CG-to-FG capacitance and of the EIS is addressed, discussing the evolution of the FG polysilicon in terms of geometry and dimensions.
IEEE Electron Device Letters 12/2010; · 2.85 Impact Factor
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ABSTRACT: This letter presents a comparison of two different variability sources for data retention of nanoscale NAND Flash memories: the neutral threshold-voltage spread and the electron-emission statistics from the floating gate. Referring to fresh cells programmed to the same threshold-voltage level, the effect of the previous dispersion contributions on the data retention transients of a memory array is evaluated. Both effects are shown to result into a broadening of the array threshold-voltage distribution with time, but a quantitative assessment clearly shows that the neutral threshold-voltage spread dominates over the electron-emission spread, revealing that cell-to-cell parameter variations represent the major source of variability for data retention in nanoscale NAND Flash memories.
IEEE Electron Device Letters 12/2010; · 2.85 Impact Factor
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ABSTRACT: This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. By means of 3-D TCAD simulations, the statistical dispersion of the threshold voltage shift induced by a single localized electron in the nitride is evaluated in presence of non-uniform substrate conduction. The role of 3-D electrostatics and atomistic doping on the results is highlighted, showing the latter as the major spread source. The threshold voltage shift induced by more than one electron in the nitride is then analyzed, showing that for increasing numbers of stored electrons a correlation among single-electron shifts clearly appears. The scaling trend and the practical impact of these statistical effects on cell operation are discussed in Part II of this paper.
IEEE Transactions on Electron Devices 10/2010; · 2.32 Impact Factor
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ABSTRACT: This paper presents experimental evidences of the granular electron injection during channel hot-electron programming of NOR Flash memories. The statistical process ruling the discrete charge transfer from the substrate to the floating gate is shown to introduce a fundamental spread contribution to the programmed threshold-voltage distribution obtained by the staircase algorithm, determining its ultimate accuracy. However, the actual precision in the control of cell threshold-voltage during programming is shown to be quite far from this fundamental limitation due to random telegraph noise effects. Moreover, the scaling trend of the electron injection statistics and the random telegraph noise limitation to the accuracy of the programming algorithm shows that the latter will continue to represent the most severe constraint for the next nor technology nodes.
IEEE Transactions on Electron Devices 09/2010; · 2.32 Impact Factor
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ABSTRACT: This letter presents a detailed experimental investigation of the erase transients of decananometer NAND Flash memories, showing a drop and then a recovery of the erase efficiency as the erase bias is increased. The modulation of the erase efficiency is studied as a function of the erase time, temperature, and the number of applied pulses: Longer erase times or higher temperatures are shown to reduce the efficiency drop, while this is enhanced when the erase pulse is split into a sequence of short pulses. Experimental evidences are explained as a result of the deep-depletion condition that exists in the floating-gate polysilicon for moderate erase biases and short erase times, reducing the electric field in the tunnel oxide and the electron-tunneling current discharging the floating gate.
IEEE Electron Device Letters 08/2010; · 2.85 Impact Factor
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S.M. Amoroso,
A. Mauri,
N. Galbiati,
C. Scozzari,
E. Mascellino,
E. Camozzi,
A. Rangoni,
T. Ghilardi,
A. Grossi,
P. Tessariol, C.M. Compagnoni,
A. Maconi,
A.L. Lacaita,
A.S. Spinelli,
G. Ghidini
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ABSTRACT: In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al<sub>2</sub>O<sub>3</sub> trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al<sub>2</sub>O<sub>3</sub> charge storage modifies program and erase saturation level particularly when higher Al<sub>2</sub>O<sub>3</sub> thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al<sub>2</sub>O<sub>3</sub> trapping. Moreover, Al<sub>2</sub>O<sub>3</sub> layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: This work investigates the variability effects on the threshold voltage distribution of deca-nanometer NAND Flash memories. Different sources of variability have been considered, evaluating their impact on the neutral, programmed and erased distributions. A compact model that is able to account for the variability effects on the array performance and reliability is presented and used. Monte Carlo simulations have been employed to analyze the contributions of variability when technology nodes scale down and to compare the intrinsic variability with the electron injection statistical fluctuations. A good agreement with experimental data is reached, opening the application of the proposed methodology to investigate the reliability impact of variability on future technology nodes.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: This paper presents a detailed experimental investigation of the cycling-induced threshold voltage instability of deca-nanometer NAND Flash arrays, focusing on its dependence on cycling time and temperature. When the array is brought to a programmed state after cycling, instability mainly shows up as a negative shift of its threshold voltage cumulative distribution, increasing with time and resulting from partial recovery of cell damage created in the previous cycling period. The threshold voltage loss displays a strong dependence not only on the tunnel oxide electric field during retention, but also on the cycling conditions. In particular, performing cycling over a longer time interval or at higher temperatures delays the threshold voltage transients on the logarithmic time axis. The delay factor is studied as a function of the cycling duration and temperature on 60 and 41 nm technologies, extracting the parameter values required for a universal damage-recovery metric for NAND.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: This paper presents a new cell crosstalk effect in deca-nanometer nand Flash memories, making the data retention and erase transients of fresh cells dependent on the threshold-voltage level at which adjacent cells in the array are placed. In particular, a programmed cell is shown to display a larger threshold-voltage loss when its adjacent cells are in the erased than in the programmed state, with cells on the same bit line and word line having a similar impact on the acceleration of the threshold-voltage loss. The effect is explained by means of 3-D TCAD simulations, showing that a low threshold voltage for the adjacent cells increases the discharging tunneling current of the monitored cell for a fixed negative potential of its floating gate. This is due to a change of the electric field profile at the corners of the monitored cell active area when the potential of the floating gate of its neighboring cells is modified.
IEEE Transactions on Electron Devices 02/2010; · 2.32 Impact Factor
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ABSTRACT: This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.
IEEE Transactions on Electron Devices 10/2009; · 2.32 Impact Factor
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ABSTRACT: This letter presents a detailed investigation of the random telegraph noise (RTN) effects on the threshold-voltage distribution of flash memory arrays programmed by the staircase algorithm. RTN is shown to introduce an exponential tail above the program verify level when considering the cell threshold voltage that ends the program operation. In addition, when a subsequent read operation is considered, a clear exponential tail is shown to appear even below the program verify level. We present a simple analysis that is able to predict the threshold-voltage distribution width accounting for both these enlargement contributions, defining practical formulas for the programming accuracy as a function of the staircase step amplitude and the RTN distribution.
IEEE Electron Device Letters 10/2009; · 2.85 Impact Factor
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ABSTRACT: This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca-nanometer Flash memories, considering both the nor and the nand architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca-nanometer Flash memories.
IEEE Transactions on Electron Devices 09/2009; · 2.32 Impact Factor
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ABSTRACT: This work investigates for the first time charge-granularity effects during channel hot-electron programming of NOR flash memories, comparing the granular electron injection and the random telegraph noise limitations to the accuracy of the programming algorithm. The spread of the threshold voltage shift that is determined by the electron injection statistics is studied as a function of the channel hot-electron programming conditions, explaining the results by an analytical model accounting for the sub-Poissonian nature of the electron transfer to the floating gate. The scaling trend of the injection statistical spread is then investigated on NOR technologies ranging from 180 to 45 nm and its contribution to the width of the threshold voltage distribution in presence of a program verify level is separated from that given by random telegraph noise.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
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ABSTRACT: We present a new physics-based model able to reproduce the program/erase transients in TANOS memories, accurately describing the charge trapping/detrapping dynamics in the nitride layer. Modeling results are extensively validated against a large number of experimental data taken on samples with different gate stack compositions, considering a quite extended range of program/erase voltages and times. The good agreement between experimental and simulated results makes the developed model a useful tool for the assessment of the performance achievable by the TANOS technology.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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ABSTRACT: We present a thorough investigation of the random telegraph noise scaling trend for both NAND and NOR floating-gate flash memories, including experimental and physics-based modeling results. The statistical distribution of the random telegraph noise amplitude is computed using conventional 3D TCAD simulations, establishing a direct connection with cell parameters. The analysis results in a simple formula for the random telegraph noise amplitude standard deviation as a function of cell width, length, substrate doping, tunnel oxide thickness and drain bias. All the simulation results are in good agreement with experimental data and are of utmost importance to understand the random telegraph noise instability and to control it in the development of next generation flash technologies.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
